similar to: [LLVMdev] Simplifing the handling of pre-legalize vector nodes

Hello, Here's a quick update on where I'm at with the pre-legalize vector changes I'm working on. I hope to have an updated patch ready to a few days, assuming I don't get too busy with other projects going on. Here are some of the issues I've come across so far. Putting the table for extended ValueTypes in SelectionDAG seems quite involved. There are a lot of places that use

After doing a bunch of work for moving pre-legalize extended ValueTypes into a table in SelectionDAG, I may have just found a simpler approach. There are under 32 simple ValueType values, so we only really need 5 bits to represent those. ValueType is already a 32-bit type on most hosts; what if we make use of the remaining 27 bits instead of using an external table? If we can assume that vector

On Mon, 11 Jun 2007, Dan Gohman wrote: > Here's a quick update on where I'm at with the pre-legalize vector changes > I'm working on. I hope to have an updated patch ready to a few days, assuming > I don't get too busy with other projects going on. Here are some of the issues > I've come across so far. Great! I'm going to reorder your email a bit to suit my

On Mon, Jun 11, 2007 at 03:39:40PM -0700, Chris Lattner wrote: > On Mon, 11 Jun 2007, Dan Gohman wrote: > > Also, CopyToReg and CopyFromReg lowering/legalization rely on being able to > > create vector-of-vector types. For example, an <8 x double> vector is bitcasted > > to (effectively) <4 x <2 x double>> for x86, allowing EXTRACT_ELEMENT to pull > >

On Jun 22, 2007, at 11:06 AM, Dan Gohman wrote: > After doing a bunch of work for moving pre-legalize extended > ValueTypes > into a table in SelectionDAG, I may have just found a simpler > approach. > > There are under 32 simple ValueType values, so we only really need > 5 bits > to represent those. ValueType is already a 32-bit type on most > hosts; what >

Is there an easy way to get the MVT::ValueType of a MachineInstruction MachineOperand? For example, the register operand of an x86 MOVAPD should have an MVT::ValueType of v2f64. A MOVAPS register operand should have an MVT::ValueType of v4f32. So given a MachineInstruction and its MachineOperands is there some easy way to derive this information? I don't see anything in TargetInstrInfo

On Sep 2, 2008, at 10:42 AM, David Greene wrote: > Is there an easy way to get the MVT::ValueType of a MachineInstruction > MachineOperand? For example, the register operand of an x86 MOVAPD > should > have an MVT::ValueType of v2f64. A MOVAPS register operand should > have an > MVT::ValueType of v4f32. The short answer is no. A op of a number of different VTs can map to

On Tuesday 02 September 2008 16:47, Evan Cheng wrote: > On Sep 2, 2008, at 10:42 AM, David Greene wrote: > > Is there an easy way to get the MVT::ValueType of a MachineInstruction > > MachineOperand? For example, the register operand of an x86 MOVAPD > > should > > have an MVT::ValueType of v2f64. A MOVAPS register operand should > > have an > >

On Feb 12, 2007, at 1:41 AM, Christopher Lamb wrote: > > selector refused to select certain ops (specifically stores) for some > instructions when the operand type wasn't the first type for the > register class. After some digging around I seem to have solved the > problem by creating bitconvert patterns between the types in the > register class like the following: > >

On Monday 18 June 2007 19:02, Christopher Lamb wrote: > Take a look at getPhysicalRegisterRegClass( > const MRegisterInfo *MRI, > MVT::ValueType VT, > unsigned reg) > > in ScheduleDAG.cpp. Yuck. I was afraid of that. What is the ValueType needed for? Isn't the register id itself an indication of the ValueType it represents? Where I'm at I

Has any one been successful with a 16-bit target? I'm new to LLVM and am having problems. One problem I found stems from code in lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp: visitRet(): // If this is an integer return value, we need to promote it ourselves to // the full width of a register, since getCopyToParts and Legalize will use // ANY_EXTEND rather than sign/zero. // FIXME:

I would like to apply the attached patch which changes MVT::ValueType (currently a uint32_t) into a one-element struct (the element being a uint32_t). This makes it harder to misuse MVT::ValueType. Thanks to this patch I found two cases in which the arguments to DAG.getConstant were inverted and one in which getStore was being passed an ValueType for the "volatile" argument. When I

Michel Salim wrote: > On Fri, Feb 6, 2009 at 8:42 PM, Tanya Lattner <tonic at nondot.org> wrote: >> LLVMers, >> >> The 2.5 pre-release is available for testing: >> http://llvm.org/prereleases/2.5/ >> > I'm updating the Fedora packaging of LLVM, and with the 02/20 > prerelease it fails to build on ppc64: > >

That recent X86 bug isn't unique to the intrinsic. We generate the same code from this which uses the shuffle sequence the vectorizers generated before the reduction intrinsics existed. declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)· declare void @TrapFunc(i64) define void @parseHeaders(i64 * %ptr) { %vptr = bitcast i64 * %ptr to <2 x i64> * %vload = load

Take a look at getPhysicalRegisterRegClass( const MRegisterInfo *MRI, MVT::ValueType VT, unsigned reg) in ScheduleDAG.cpp. -- Christopher Lamb On Jun 18, 2007, at 4:52 PM, David A. Greene wrote: > How do I get the TargetRegisterClass for a physical register? > SSARegMap::getRegClass only works for virtual registers. > >

On Fri, Feb 6, 2009 at 8:42 PM, Tanya Lattner <tonic at nondot.org> wrote: > LLVMers, > > The 2.5 pre-release is available for testing: > http://llvm.org/prereleases/2.5/ > I'm updating the Fedora packaging of LLVM, and with the 02/20 prerelease it fails to build on ppc64: http://koji.fedoraproject.org/koji/taskinfo?taskID=1148023 make[1]: Entering directory

No we still use the shuffle expansion which is why the issue isn't unique to the intrinsic. ~Craig On Thu, Apr 9, 2020 at 10:21 AM Amara Emerson <aemerson at apple.com> wrote: > Has x86 switched to the intrinsics now? > > On Apr 9, 2020, at 10:17 AM, Craig Topper <craig.topper at gmail.com> wrote: > > That recent X86 bug isn't unique to the intrinsic. We

llvm[3]: Compiling SPUISelDAGToDAG.cpp for Debug build In file included from /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/ SPUISelDAGToDAG.cpp:334: /Volumes/mrs5/net/llvm/llvm-build/lib/Target/CellSPU/ SPUGenDAGISel.inc: In member function ‘llvm::SDNode* SPUDAGToDAGISel::Emit_5(const llvm::SDOperand&, unsigned int, unsigned int, llvm::MVT::ValueType, llvm::MVT::ValueType)’:

Hi All, I'm working on a back end for an architecture that makes use of multi- typed register classes. def MR: RegisterClass<"namespace", [type1, type2, ... ], ... > When running some preliminary tests I found that the instruction selector refused to select certain ops (specifically stores) for some instructions when the operand type wasn't the first type for the

Hi, I'm porting some existing code of mine to CVS HEAD, and don't understand something about new RegisterClass TableGen definition: class RegisterClass<string namespace, list<ValueType> regTypes,........ { ..... string Namespace = namespace; What is this "namespace" thing? It looks like it should contain the name of backend, right? // RegType