similar to: [LLVMdev] strange pass behaviour

Displaying 20 results from an estimated 400 matches similar to: "[LLVMdev] strange pass behaviour"

2006 Jun 01
2
[LLVMdev] Adding an object to llc (analysis pass)
Hi > Right it does. However, does something *else* require MParSchedule? If > so, what? Ok, i am writing on a different backend based on the cbackend. The test usage of this pass looks like this: void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<LoopInfo>(); AU.addRequired<MParSchedule>(); AU.setPreservesAll(); } and then in the
2006 May 30
3
[LLVMdev] Adding an object to llc (analysis pass)
Hi > One would expect this, its a facility of the C++ language. The anonymous > namespace is, essentially, the same as declaring everything in it > static. That is, the symbols are not exported and not available for > linking. Yes, it was pretty clear after finding out that this isn't a linking error which i suspected... > > So for all those trying to add an analysis path:
2006 May 31
2
[LLVMdev] Adding an object to llc (analysis pass)
Hi Am Dienstag, 30. Mai 2006 19:21 schrieb Chris Lattner: > On Tue, 30 May 2006, Silken Tiger wrote: > > Everthing now compiles fine, but when running llc with invoking my own > > backend derived from the cbackend i get the following error: > > namespace llvm { > > class MParSchedule : public BasicBlockPass { > > public: > > > >
2006 May 31
0
[LLVMdev] Adding an object to llc (analysis pass)
On Wed, 31 May 2006, Silken Tiger wrote: >> that requires a BasicBlockPass, it will fail the same was as when a >> ModulePass requires a FunctionPass. > void MParSchedule::getAnalysisUsage(AnalysisUsage &AU) const { > AU.setPreservesAll(); > } > > MParSchedule requires nothing and changes nothing. So hopefully the above code > represents this fact? Right
2006 May 30
0
[LLVMdev] Adding an object to llc (analysis pass)
On Tue, 30 May 2006, Silken Tiger wrote: > Everthing now compiles fine, but when running llc with invoking my own backend > derived from the cbackend i get the following error: > namespace llvm { > class MParSchedule : public BasicBlockPass { > public: > This pass has been tested as optimization pass with opt, and everything worked > in this
2012 Jun 19
1
[LLVMdev] llvm::Triple error in new backend
Hi, I try to write a new backend. At the moment I run into a compiler error and don't know how I can solve this problem. Like several other targets I have a file 'mybackendTargetInfo.cpp' in the subdirectory 'TargetInfo'. The content of this file is: #include "mybackend.h" #include "llvm/Module.h" #include "llvm/Support/TargetRegistry.h" using
2006 Jun 01
0
[LLVMdev] Adding an object to llc (analysis pass)
On Thu, 1 Jun 2006, Silken Tiger wrote: >> Right it does. However, does something *else* require MParSchedule? If >> so, what? > Ok, i am writing on a different backend based on the cbackend. Ok. > The test usage of this pass looks like this: > > void getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequired<LoopInfo>(); >
2006 May 30
0
[LLVMdev] Adding an object to llc
On Tue, 2006-05-30 at 14:48 +0200, Silken Tiger wrote: > Hi > > Thanks for all your feedback. I just found the reason for the compile failure > for my analysis pass: I had to add my object to the namespace llvm instead of > anonymous. This took me some time since i was looking for an linking > failure... but as errors go i should have looked at the error message a >
2015 Jul 22
1
[LLVMdev] prevent an SDValue from lower into an immediate field in load
Hi there, I am doing relocation in my backend by calling my function getAddrNonPic: SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG)const{ SValue Hi=getTarget(N,Ty,DAG, MyBackend::Hi16); SValue Lo=getTarget(N,Ty,DAG, MyBackend::Lo16); return DAG.getNode(ISD::ADD, DL, Ty, DAG.getNode(MyBackend::Hi16, DL, Ty, Hi), DAG.getNode(MyBackend::Lo16, DL, Ty, Ho)); }
2006 May 12
2
[LLVMdev] Instruction->mayReadFromMemory
Hi I am currently trying to schedule instructions with my own algorithm. For that i need to get the data dependency between the instructions. So currently i am dooing s.t. like: for(BasicBlock::iterator j=B.begin(),bbe=B.end();j!=bbe;++j) { InstructionList.push_back(j); if (const AllocaInst *AI = dyn_cast<AllocaInst>(j)) {
2008 Nov 25
1
[LLVMdev] AddReadAttrs vs. TargetMachine?
Hi, I want to invoke the AddReadAttrs pass with my software backend (derived from TargetMachine like CBackend). CBackend uses addPassesToEmitWholeFile-method for invoking several passes. I tried to use the same method, but it failed on runtime. Running llc with my backend produces (mac os x 10.5 and llvm 2.4): dyld: lazy symbol binding failed: Symbol not found:
2006 Jun 16
2
[LLVMdev] Adding an object to llc (analysis pass)
Hi Chris and llvm list Thanks for your answer. > So again, this is the problem I described earlier: you have a pass > (MParSchedule) which is a basic block pass. This pass is being required > by another pass (your C backend-based thing) which is not a basic block > pass. This is the problem, please see the "how to write a pass" doc. The > fix is to change
2008 Sep 22
2
[LLVMdev] Problems with written function pass
Hello, my name is Marc. I wrote a llvm function pass by using the "hello world" tutorial. But this selfwritten pass (GA_VHDL_Pass) dependes on another function pass (GenomePass). GenomePass also dependes on two other function passes. The Pass GenomePass generates an object, which is used in my GA-VHDL_Pass. When I compile my Make file I always get this error message:
2012 May 07
1
[LLVMdev] TableGen backend API refactoring.
tl;dr: is anyone opposed to making the interface to a TableGen backend be: void MyBackend(RecordKeeper &, raw_ostream & /* maybe some other args, per backend's needs */); ?? Currently, this is the "interface" for a TableGen backend: struct TableGenBackend { virtual void anchor(); virtual ~TableGenBackend() {} // run - All TableGen backends should implement the run
2005 Oct 15
1
[LLVMdev] Dump instruction list prior register allocation
Hi there, I have a question on the LLVM internals. Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled assembly) prior register allocation? Does LLVM use infinite (virtual) registers similar to MachSUIF? This is, of course, meant for a given target in contrast to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is possible at this point. Plus:
2009 Nov 01
0
[LLVMdev] Something wrong with my libpthread.so
Hi, On Sat, Oct 31, 2009 at 11:42 AM, Nan Zhu <zhunansjtu at gmail.com> wrote: > Hi,all > > I tried to run the generated whole-program bitcode of BIND,but I got some > information: > > 0   lli             0x0000000000feda16 > 1   lli             0x0000000000fed88f > 2   libpthread.so.0 0x0000003df340eee0 > 3   libc.so.6       0x0000003df28332f5 gsignal + 53 >
2009 Nov 01
1
[LLVMdev] Something wrong with my libpthread.so
Mahadevan R wrote: > Hi, > > On Sat, Oct 31, 2009 at 11:42 AM, Nan Zhu <zhunansjtu at gmail.com> wrote: >> Hi,all >> >> I tried to run the generated whole-program bitcode of BIND,but I got some >> information: >> >> 0 lli 0x0000000000feda16 >> 1 lli 0x0000000000fed88f >> 2 libpthread.so.0
2006 May 30
2
[LLVMdev] Adding an object to llc
Hi Thanks for all your feedback. I just found the reason for the compile failure for my analysis pass: I had to add my object to the namespace llvm instead of anonymous. This took me some time since i was looking for an linking failure... but as errors go i should have looked at the error message a little closer. So for all those trying to add an analysis path: * add the object name to the
2012 Sep 26
0
[LLVMdev] [PATCH / PROPOSAL] bitcode encoding that is ~15% smaller for large bitcode files...
Hi Jan, > I've been looking into how to make llvm bitcode files smaller. There is one > simple change that appears to shrink linked bitcode files by about 15%. See > this spreadsheet for some rough data: > > https://docs.google.com/spreadsheet/ccc?key=0AjRrJHQc4_bddEtJdjdIek5fMDdIdFFIZldZXzdWa0E the improvement is wonderful! ... > In any case, the patch is attached if
2008 Oct 13
0
[LLVMdev] Weirdness w/ llvm control flow graph generation
I am working on implementing break/continue and the flow control graphs that I am seeing are having all sorts of weird flow control that does not necessarily exist in the IR representation. For, example, a simple code segment that is a while loop w/ a continue ends up generating a CFG that is two while loops with one embedded inside each other. I've attached the dot files and the IR code. Any