similar to: [LLVMdev] variant generation question

On Fri, 9 Feb 2007, Scott Michel wrote: > I would have expected four additional patterns, each with the (and $rC, $rA) > variant in it. But I only get the above four. > > Is this a bug or a feature? :-) This is a feature. They would match the same pattern, so it would just be generating dead code. For the same reason, if you write something like: (set $rd, (and $rs, 123)) you

On Feb 9, 2007, at 7:42 PM, Chris Lattner wrote: > On Fri, 9 Feb 2007, Scott Michel wrote: >> I would have expected four additional patterns, each with the (and >> $rC, $rA) >> variant in it. But I only get the above four. >> >> Is this a bug or a feature? :-) > > This is a feature. They would match the same pattern, so it would > just be >

Evan: What you requested was in the debug output (sans offending Node), but here it is, outside of the attachment. The offending node is highlighted: SU(0): 0xa908760: ch = EntryToken SU(1): 0xa907600: i32,ch,flag = CopyFromReg 0xa9095d0, 0xa9070e0, 0xa9095d0:1 0xa906e30: ch,flag = CopyToReg 0xa908760, 0xa9070e0, 0xa9071f0 <<--<<--<<--<<--<< Node

Yup, I've got one remaining bug that holding up the CellSPU release. It still has a bunch of warts, but so long as I can get it into shape such that llvm-gcc-4.2 compiles all the way through, then we collectively have something with which to work. I'm getting the following error from llc, the attachments have llc's debug and the .ll files, respectively. Can anyone shed some

This is a scheduler assertion. It means a value (virtual register) use is somehow scheduled before its definition. Please run llc in gdb. Call dumpSchedule() to print out the schedule. Also please let me know which node it is processing at the time of the assertion. Evan On Oct 15, 2007, at 11:48 PM, Scott Michel <scottm at aero.org> wrote: > Yup, I've got one remaining bug

Sorry, still not enough information. I am guessing it's asserting in getVR() called from EmitNode()? The node is CopyToReg and it's trying to find the virtual register of operand 2? From the schedule, I don't see the definition of the operand. Can you do DAG.viewGraph()? That should gives us a better idea. Evan On Oct 16, 2007, at 9:06 PM, Scott Michel wrote: > Evan: >

Maybe it's because I've got a lot of two machine operand instructions and have to rely on the tied-to constraint, but I'm seeing a lot of dead reg-to-reg copy instructions, e.g.: ori $3, $3, 0 (Cell SPU's version of reg-to-reg copy, looks a lot like PPC, no?) Is there any way I can detect when this occurs, or is there code where this detection takes place in the target to which

I just ran across something interesting: DAGCombine inserts a 64-bit constant as the result of converting a (bitconvert (fabs val)) to a (and (bitconvert val), i64const). The problem: i64 constants have to be legalized for the CellSPU platform. DAGCombine is doing the right thing but it's not doing the right thing for CellSPU and it's damed difficult to work around this

Evan: And after legalize too. DAGCombine gets run after legalization. :-) -scooter On Jan 19, 2009, at 10:52 PM, Evan Cheng wrote: > Right. DAGCombine will insert *illegal* nodes before legalize. > > Evan > > On Jan 19, 2009, at 8:17 PM, Eli Friedman wrote: > >> On Mon, Jan 19, 2009 at 6:36 PM, Scott Michel <scottm at aero.org> >> wrote: >>> I

Not entirely sure how to categorize this particular problem, but it's clearly platform test related: "grep -w" appears to operate differently on the x86_64 linux buildbot versus my local Mac OS 10.4.11 and Ubuntu x86_64. In the CellSPU's shift_ops.ll test case, "grep -w shlh" returns the correct 9 expected occurances, whereas the x86_64 buildbot finds 10. Any

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

Dan: CellSPU could clearly benefit from the post-RA scheduler. In fact, we were thinking about writing a machine pass of our own. One thing that does "disturb" me is that both HazardRecognizer and post-RA sched assume there's only one kind of NOP. For Cell, there are two, depending upon the pipeline being filled. Pipe 0 takes "ENOP" whereas Pipe 1 take

Anton Korobeynikov wrote: >>the official cutover. Granted, you might need darcs to pull the current >>version out of its repo, since it was originally designed with darcs in >>mind. > > I can confirm, that tailor converts LLVM CVS with all history preserved > to mercurial repository without any visible troubles. I'm not sure if I just took HEAD or converted the

On 11/27/06, Scott Michel <scottm at rushg.aero.org> wrote: > Anton Korobeynikov wrote: > >>the official cutover. Granted, you might need darcs to pull the current > >>version out of its repo, since it was originally designed with darcs in > >>mind. > > > > I can confirm, that tailor converts LLVM CVS with all history preserved > > to mercurial

Right. DAGCombine will insert *illegal* nodes before legalize. Evan On Jan 19, 2009, at 8:17 PM, Eli Friedman wrote: > On Mon, Jan 19, 2009 at 6:36 PM, Scott Michel <scottm at aero.org> wrote: >> I just ran across something interesting: DAGCombine inserts a 64-bit >> constant as the result of converting a (bitconvert (fabs val)) to a >> (and (bitconvert val),

On a related note, I wrote a few scripts to detect and correct some types of such style errors, see llvm/utils/lint/* . I also added a function to llvm/utils/vim/vimrc to delete trailing whitespace and highlight existing trailing whitespace -- if anyone's an Emacs-lisp hacker, please add it to the emacs config file as well. Sure, this doesn't enforce anything, but I'm hoping folks

Ugh. Management lobotomy kicked in. Need to RTFC better. On Thu, Feb 25, 2010 at 6:18 PM, Scott Michel <scooter.phd at gmail.com> wrote: > There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs =

On Dec 30, 2008, at 4:55 PM, Misha Brukman wrote: > 2008/12/30 Scott Michel <scottm at aero.org> > Not entirely sure how to categorize this particular problem, but it's > clearly platform test related: "grep -w" appears to operate > differently on the x86_64 linux buildbot versus my local Mac OS > 10.4.11 and Ubuntu x86_64. In the CellSPU's shift_ops.ll test

There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true; break; }

I was able to resolve my previous question about dealing with custom loads/stores, and following Chris' suggestion, the IBM Cell SPU backend can generate code for "int main(void) { return 0; }" without crashing llc. There's a lot of work still to be done... like getting frame offsets correctly computed and hauling in the raft of intrinsics that the Cell SDK defines. Three quick