similar to: [LLVMdev] a pseudo instruction - code modified

I'd like to implement "reg" instruction on my new architecture. This is kinda pseudo instruction do not generate hardware directly but make hardware to be generated indirectly. If I code a simple function like this: void sum(int i, int j) { int k; k = i + j; } On the assembly mnemonics, it should be shown as follows: Enter sum; reg k add i,j;k Exit sum; I haven't

Hello. I have a very simple code like this: int sum(int i, int j) { int k; k = i + j; } #ifdef LINUX #include <stdio.h> #include <stdlib.h> int main () { int k; k = sum(3,4); return k; } #endif If I emit this to SPARC assembly mnemonics through LLVM, it is shown as follows

Thank you so much for this info. That's exactly what I want. But, I'm still not sure about using -g. Let me imagine I am modifying x86 assembly instructions and trying to test it with 'hello.c' to check out the assembly is properly emitted. I should type "$ llvm-gcc hello.c -o hello" to have the bytecode of 'hello.c'. And then I can have an x86 assembly mnemonics

Thank you for reminding me the notion of the basic block. Of course, I know all the assembly takes the form of BBs and is divided into units of BB. OK. It looks better for me to explain what I wanted to do more clear from the first. Actually, I am working on emitting out an assembly of VM by using LLVM. LLVM assembly looks similar with this VM assembly except BB. The VM assembly does not have the

I have this same problem in our backend. I solve it by adding a pseudo instruction at instruction selection that transforms @R1 into R1, so only a single pattern is required. I then can propogate the pseudo instruction after instruction selection. Micah From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Lu Mitnick Sent: Tuesday, January 18, 2011 10:29 AM

Hello Villmow, Is it your backend EFI Byte Code Virtual Machine?? Would you mind to give me an example about what pseudo instruction you add?? thanks a lot yi-hong 2011/1/19 Villmow, Micah <Micah.Villmow at amd.com> > I have this same problem in our backend. I solve it by adding a pseudo > instruction at instruction selection that transforms @R1 into R1, so only a > single

Hello all, I am at the adding Instruction Set stage of adding new target support into LLVM. There is a single instruction op mnemonic with multiple operand forms. For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the solution of x86 is adding suffix of instruction and translating instruction op

Hello. My name is Seung Jae Lee. I'd like to ask you onething about converting to ARM assembly code. I saved the simplest C code shown in your LLVM webpage as 'hello.c' And I made 'hello.bc' by "$ llvm-gcc hello.c -o hello". In order to make ARM assembly code, I typed "llc -march=arm hello.bc -o hello.arm" But, I met this error. llc: ARMISelDAGToDAG.cpp:73:

Xi, I just installed VS2005 pro w/ SP1 for Win Vista. Thanks, Seung ---- Original message ---- >Date: Fri, 22 Feb 2008 12:36:43 +0800 >From: "Xi Wang" <xi.wang at gmail.com> >Subject: Re: [LLVMdev] Is there someone tried LLVM 2.1 on Visual Studio 2005? >To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > >I'm sorry but did you

Hi Amara, Thanks for your suggestions. I have made the changes you suggested and added a new test to check that we print an error when parsing a non-ldr mnemonic with an operand containing `=`. The updated patch is attached. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: Amara Emerson

Hello. I am making a backend for a virtual machine. But it does assume infinite number of virtual registers unlike those of usual machines. In this case, how can I implement this? Would you mind telling me some tips? Thank you so much. Seung Jae Lee

Hello, guys. I just tested -reg2mem pass to see how it changes my bitcode. E.g., for the following simple C code: ------------------------------------------------------------- int foo() { int i,j; int sum = 0; for (i=0; i<10; i++) { sum += i; for (j=0; j<3; j++) sum += 2; } return sum; } ------------------------------------------------------------- I could get the

Hello. I am making a LLVM backend for a new architecture XCC. During implementation of instructions for XCC, I found that there are instructions need more than 3 operands in the target language manual. I could implement insructions need 1, 2 or 3 operands thanks to the examples in the LLVM backends already offered by you guys. But, I am not sure about those kind of instructions needs many number

Dear Mr. Cheng: Thank you for kind information. Can you tell me in more detail about that? For example, I am trying to implement 'demultiplex' instruction as follows: demultiplex <multiplexid,choose,branch0id,branch1id,…,otherwisebranchid> In this case, the number of branch#id is not definite. It can be 1, 2, 3...or any number. My question was about this. I am still not sure how

On the document about writing an LLVM backend, I became to wonder what the 'virtual register' is in the following statement. "You also need to define register classes to contain these registers, such as the integer register class and floating-point register class, so that you can allocate virtual registers to instructions from these sets, and let the target-independent register

Hi David, Thanks for your efforts here. I have a few comments on your patch, although I realise it's still a work in progress. +class ConstantPool { + MCSymbol *Label; + typedef std::vector<const MCExpr*> EntryVecTy; Use a SmallVector here? + MCSymbol *getLabel() {return Label;} + size_t getNumEntries() {return Entries.size();} + const MCExpr *getEntry(size_t Num) {return

Dear Mr. Lattner: Thank you for kind information. I am still a little confused, though. In your example, %X = add int %Y, %Z is generated to add EAX, EBX I think EAX and EBX are the register names of X86. But, I should emit variable names instead of register names. For my example in the source code, int k; k = i + j; should be emit like this: reg k add i,j;k (If

Dear Mr. Lattner: You have asked me how my instruction set works. If I code like this: int foo1() { int x1,x2; x1 =1; x2 = foo2(x1); return x2; } int foo2(int k) { if(k == 1) k = 2; return k; } int main () { int j; j = foo1(); } This should be emitted like this: Enter foo1; reg x2, x1 add 1;x1 Call foo2;x1,x2 Exit foo1; x2

Hi, I'd like to define a pseudo-instruction whose expansion will, as a side-effect, overwrite an input register's value: the pseudo-instruction ldw r1:r2, P to load 2 bytes from memory address P is to be expaneded to ld r1, P+ ld r2, P where "ld _, P+" is an instruction that loads a single byte from P, and post-increments P by one. How can I represent this behaviour in

Dear Prof.Adve and Bill, I deeply appreciate your comments and concerns. (Please forgive my late response. I've tried some more cases to make this issue) As Prof.Adve mentioned, I need to explain exactly what my problem is, but I have no good ability that I can explain it in this plain text space. For this reason, I made a .pdf file and linked it as follows: