I'd like to implement "reg" instruction on my new architecture.
This is kinda pseudo instruction do not generate hardware directly but make
hardware to be generated indirectly.
If I code a simple function like this:
void sum(int i, int j)
{
int k;
k = i + j;
}
On the assembly mnemonics, it should be shown as follows:
Enter sum;
reg k
add i,j;k
Exit sum;
I haven't seen any part dealing with this kind of instruction in the LLVM
backend example codes.
Can you give me a tip about how to start with?
Thank you very much.
Seung Jae Lee
On Fri, 2 Feb 2007, Seung Jae Lee wrote:> I'd like to implement "reg" instruction on my new architecture. This is > kinda pseudo instruction do not generate hardware directly but make > hardware to be generated indirectly. > > If I code a simple function like this: > On the assembly mnemonics, it should be shown as follows:The canonical way to do this is to add a new target-specific llvm intrinsic. This is the way that the X86 and PPC backends support all the SSE/Altivec instructions. Take a look at include/llvm/Intrinsic* for some info. -Chris -- http://nondot.org/sabre/ http://llvm.org/