similar to: [LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND"

2006 May 30
0
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
On Tue, 30 May 2006, [UTF-8] Rafael Esp?ndola wrote: > I have changed the way in which the ARM backend generates a function > return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now > expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch > is attached. Ok, I haven't looked at the code, but you're free to do whatever make sense. > In my
2006 May 31
2
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
> > Why it is named RETFLAG? > > Historical reason. Originally we didn't have nodes that could > *optionally* have an input flag. A better design, e.g. on PPC would be to > have a PPCISD::RET node, which takes an optional input flag, and always > lower RET to it. I See. I will try to always lower to "(mov)*;bx lr" on ARM. > Flag in the SelectionDAG stuff is
2006 May 31
1
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
On 5/31/06, Chris Lattner <sabre at nondot.org> wrote: > On Wed, 31 May 2006, [UTF-8] Rafael Esp?ndola wrote: > >> We don't want the copy and shift to wander apart from each other (e.g. we > >> don't want another shift to get scheduled in between them), so we flag > >> them together. In practice, these copies usually get coallesced away. > > In
2006 May 31
0
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
On Wed, 31 May 2006, [UTF-8] Rafael Esp?ndola wrote: >> We don't want the copy and shift to wander apart from each other (e.g. we >> don't want another shift to get scheduled in between them), so we flag >> them together. In practice, these copies usually get coallesced away. > In the second case shl explicitly uses CL. Shouldn't the register > allocator be
2006 Aug 02
1
[LLVMdev] adding an optional flag edge to a BRIND node
Is there any way to add an optional flag edge to a BRIND node? I In the ARM backend I lower returns directly to BRINDs, so I need to add an edge connecting the BRIND and the CopyToReg that sets the return value. The other option is to create an ARM specific node that is identical to BRIND except for having a flag edge. Thanks, Rafael
2006 May 17
1
[LLVMdev] matching "ret 0"
I am trying to make the ARM backend compile int f() {return 0;} I have added a custom expansion of ret that is similar to the one used in ppc and sparc. If I understand it correctly, it will expand the ret into an assignment to the return register (R0) and a RETFLAG node. I declared the bx instruction to match RETFLAG. Now the instruction selection says it can't match " i32 = Constant
2007 Jan 11
1
[LLVMdev] Pattern matching questions
On Jan 9, 2007, at 5:23 PM, Scott Michel wrote: > Chris Lattner wrote: >>> It is possible to write multi-instruction pattern, e.g. >>> X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>> Sounds like you want to define them as SDNodeXform that returns >>> upper >>> and lower 16 bits respectively. Take a look at PSxLDQ_imm in
2007 Jan 10
0
[LLVMdev] Pattern matching questions
Chris Lattner wrote: >>It is possible to write multi-instruction pattern, e.g. >>X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>Sounds like you want to define them as SDNodeXform that returns upper >>and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC
2006 Aug 03
1
[LLVMdev] need some help to remove a dummy mov
I have just added a retflag to the ARM backend. I thought that using BRIND directly was to blame for a dummy move. But I the move wasn't removed. When compiling --------------------------------------- int %g() { entry: call void %f( ) ret int 42 } declare void %f() -------------------------------------- The ARM backend produces ------------------------------------------- g:
2020 Jun 08
2
Mitigating straight-line speculation vulnerability CVE-2020-13844
Hi, A new speculative cache side-channel vulnerability has been published at https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/downloads/straight-line-speculation, named "straight-line speculation”, CVE-2020-13844. In this email, I'd like to explain the toolchain mitigation we've prepared to mitigate against this vulnerability for AArch64.
2018 Feb 16
0
CopyToReg node
Hi all, I'm having some trouble with x86 generating some CopyToReg nodes with a null 2nd operand. I've done an extensive search of the entire codebase and found that all creation of CopyToReg nodes happens at SelectionDAG.h, eventually, but my debug messages did not register a call to either of the three getCopyToReg methods it provides. Is there any other place where CopyToReg nodes get
2015 Jan 27
2
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
I have a CopyToReg that is copying from different size types, what's the best way to change that to a zext or sext node based on signed or unsigned? I'm fairly unfamiliar with SelectionDAG process (outside of the docs on llvm website). It seems like I should be able to insert a custom hook using the register class to identify the type, potentially in ISelDAGToDag.cpp or is there a better
2012 Dec 09
0
[LLVMdev] PHI instructions without CopyFromReg/CopyToReg
In my target I want to have mem-mem operations. But PHI instructions use virtual registers and gets converted to a series of CopyFromReg and CopyToReg instructions. These DAGs end up using physical registers. My first approach was to spill the virtual register to force a mem-mem operation. But I was unable to do this using LowerOperation() and setOperationAction(ISD::CopyToReg, MVT::i32, Custom);
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
So there's a DAG that looks like this in the debug output: Selecting: t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127> In the instruction selection phase, what pattern would that match? I've constructed this so far: (??? REG16:$dst, i16imm:$src) but the problem is, I can't determine what to use as ???. There is an ISD::CopyToReg enum value, but I don't
2015 Jan 27
2
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
Thanks for getting back to me. So those nodes record if the type has already been expanded from a narrower type. Can you elaborate how I could use these to help? Again, I'm pretty unfamiliar with the SDNodes. Thanks. On Tue, Jan 27, 2015 at 3:22 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 01/27/2015 12:16 PM, Ryan Taylor wrote: > > I have a CopyToReg that
2018 May 30
2
InstrEmitter::CreateVirtualRegisters handling of CopyToReg
Hi, I wonder if anyone has any comment on a patch like: diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 65ee3816f84..4780f6f0e59 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -243,18 +243,21 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,      if (!VRBase &&
2015 Jan 27
4
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
I have a CopyToReg that is moving a 16bit reg to a 32bit reg, it's currently being mapped out as a simple mov (not an ext), I would like to change that to an ext. It seemed that the SelDAG was the easiest and cleanest way to do this. I can change the mov to an extension MI in the .td file; however, I can't tell at that point whether it's a sext or a zext, so it seemed the SelDAG was
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
Hmm, okay. Then what's the problem being reported here? I'm not sure what I'm supposed to do with "LLVM ERROR: Cannot select: t1: i16 = Constant<127>".BTW, the function is: ; ModuleID = 'return.c' source_filename = "return.c" target datalayout = "E-m:e-p:16:16:16-i1:16:16-i8:16:16-i16:16:16-i32:16:16-i64:16:16-S16-n16" target triple =
1997 Dec 23
1
Junk e-mail .... help needed!!!
Hi!! Of late, I'm getting a lot of un-solicited mails from this list, and inspite of un-subscribing mails, messages, threats , nothing really seems to work... My question: 1. Is there any way I can 'avoid' or 'bounce' incoming messages at the mail-server level?? 2. I cannot change my address (alias) as such... since this involves sending reminders to God knows how many
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
Well, that's the thing: I thought that was CopyToReg. I don't know what the name of the node is to load one value into a register, so I don't know how to construct such a pattern. On Sat, Nov 4, 2017 at 9:23 PM Craig Topper <craig.topper at gmail.com> wrote: > Do you have a pattern for loading an i16 immediate into a 16-bit register? > > ~Craig > > On Sat, Nov 4,