similar to: [LLVMdev] doc error?

Hi all, Our target does not have native support for 64-bit integers, so we rely on library calls for certain operations (like sdiv). We recently ran into a problem where these operations that are expanded to library calls aren't maintaining the proper ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2:

Hi everyone, I have the following code (as part of a larger function): %0 = icmp eq i16 %a, 0 ; <i1> [#uses=1] br i1 %0, label %bb1, label %bb I would like to match this with a BRCOND, but all I get is an error message when compiling the above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19]

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

Hello. I'm having problems at instruction selection with my back end with the following basic-block due to a vector add with immediate constant vector (obtained by vectorizing a simple C program doing vector sum map): vector.ph: ; preds = %vector.memcheck50 %.splatinsert = insertelement <8 x i64> undef, i64 %i.07.unr, i32 0

i'd like to know what progress you guys have made (not on cvs?). i don't want to re-invent wheels, and the existing many code generator generators. i am evaluating many possbile code generation libraries. at present i give me preferrence to "Prop": http://www.cs.nyu.edu/leunga/www/prop.html and it's portable too. are there any other good library you could recommend?

also i further run the following command; llc -debug filer-knl_o3.ll and its output is attached here. by looking at the output can we say that legalization runs fine and the error is due to instruction selection/ pattern matching which is not yet implemented? so do i need to worry and try to correct it at this stage or should i move forward to implement instruction selection/ pattern matching?

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

guys, 1)i made a mistake in my post. the said TF node was created when Selected() was called in ADDC node. 2) the source code under test short a,b; void test() { a+=b; } 3)the DAG after ADDC was seleced: Select node: 0x4977a20: ch,glue = <<Unknown Machine Node #65419>> 0x4972bd0, 0x49731d0, 0x4976c20, 0x49730d0<Mem:LD1[@a](align=2)> Result node: 0x4977a20: ch,glue =

the proposed architecture (chris) doesn't seem to attack the phase ordering problem. through having independent instruction selection, instruction scheduling, and register allocation phases faciliate a modular design, but i believe the phase-coupled code generator generator high quality code on many architectures. espeically in the embedded system like a media/dsp processors with very limited

Hi All, I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I have a llvm IR code snippet as following: llvm IR code snippet: for.body: ; preds = %entry, %for.cond %i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ] %0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23> %1 = extractelement <2 x i1>

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available

On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote: > http://portal.acm.org/citation.cfm?id=75700 Oh, tWig. :) Yes, tree pattern matching is exactly the direction we are heading. We are slowly making the code generators more and more automatically generated as time goes on. The SelectionDAG infrastructure is mean to support exactly this (perform Tree or DAG pattern matching on the optimized DAG

On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote: > i'd like to know what progress you guys have made (not on cvs?). Everything is in CVS. Noone is currently working on automating the pattern matching generator process yet. Before doing that, there are a few changes we want to make to the SelectionDAG interface. In particular, right now, the selection process basically works like this: #1.

Hi all, When compiling some programs using the Mips backend i'm getting this assert message on lib/CodeGen/LiveInterval.cpp:227: "Range is not entirely in interval!" I don't know yet if it's something that is missing on the backend code or why the range to be removed it outside the interval, does anyone have any clue? A more detailed output is attached. The program i tried

> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question

I cannot understand what does the paragraph mean. Could anyone please elaborate it? http://llvm.cs.uiuc.edu/ChrisLLVM/docs/CodeGenerator.html#selectiondag_legalize "Instead of using a Legalize pass, we could require that every target-specific selector supports and expands every operator and type even if they are not supported and may require many instructions to implement (in fact, this is

On Friday 03 October 2008 12:06, Dan Gohman wrote: > On Fri, October 3, 2008 9:10 am, David Greene wrote: > > On Thursday 02 October 2008 19:32, Dan Gohman wrote: > >> Looking at your dump() output above, it looks like the pre-selection > >> loads have multiple uses, so even though you've managed to match a > >> larger pattern that incorporates them, they

I have added new instructions to my target, unfortunately they are not being properly type legalized. The instructions I've added are a vector add, vector load and a vector store. Can anyone lend a hand on how to legalize them so that my target would be able to recognize them. Below is the output of llc with a -debug-only=isel. As you could see the output type for load, store, and add changes

i'd like to know if there is any plan or existing work to add a Aho's trig language like code generator generator? "...If you are starting a new port, we recommend that you write the instruction selector using the SelectionDAG infrastructure." any other things i should know before i write one? thank you.

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce