similar to: [LLVMdev] SparcV9 casa instruction

Hi, I need to implement the compare and swap instruction in the Sparc backend. It has the form: casa [reg]imm, reg, reg I believe I have specified it correctly in SparcV9Instr.def: I(CASAi, "casa", 4, -1, B12, true, 0, 1, SPARC_SINGLE, M_LOAD_FLAG|M_STORE_FLAG) Is this correct? And how do I specify the above syntax in SparcV9InstrInfo.td? Brent

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Hi, I need to generate a branch instruction from within CodeGenIntrinsic in SparcV9BurgISel.cpp. I generate a few instructions and add them to the mvec vector, and then I need to generate a branch whose target is the first instruction in the vector. I've seen how other portions of the code do this, but they have access to more information than CodeGenIntrinsic. Thanks, Brent

Hi! I can't build LLVM using GCC 4.1 (GCC CVS mainline) after http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050328/025003.html Build terminated with error: /home/wanderer/pkg/build/llvm/src/llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:25: error: explicit qualification in declaration of `llvm::FunctionPass* llvm::createDependenceAnalyzer()' at line:

Hi: When I tried to use llc -march=sparcv9 to compile some llvm .bc to SparcV9, I got such error: llc: /llvm/lib/Target/SparcV9/SparcV9RegInfo.h:62: virtual void llvm::TargetRegClassInfo::markColorsUsed(unsigned int, int, int, std::vector<bool, std::allocator<bool> >&) const: Assertion `UserRegType == RegTypeWanted && "Default method is probably incorrect for

Hi: In the file of SparcV9BurgISel.cpp, you said you didn't implement the "Switch" instruction and I also can't find how the "Select" instruction is implemented. So do you do some work to handle these two kind of instructions in other parts? Where can I find it? Thank you! -- Shuhan

Hello, Nathan >   I've put together some preliminary patches to add frontend support for the sparcv9-* subtarget (ie 64-bit SPARC), modelled on the corresponding x86-64 code - do these look reasonable for inclusion? This doesn't address the codegen side of things yet (isel falls over when trying to actually emit 64-bit code), but at least bitcode generation looks correct now. Tested on

Hello, Nathan >   I may need to clarify, sparcv9-* is used for the SPARCV9 ABI (ie 64-bit ABI), rather than the SPARCV9 CPU per se. It serves the same purpose as x86_64-* and powerpc64-*, which is to say it's associated with -m64, not -mcpu=v9 (although unsurprisingly -m64 does require a V9 or later CPU). I may be wrong, but I think the only distinction in ARM is between arm and thumb

Hi, all, I have been recently porting a backend for our experimental DSP. It has a regular register file for ALU, naming it R registers, and another register file (J registers) for memory access. Both R registers and J registers are 32-bit. Since LLVM cannot distinguish 32-bit integers or pointers during register allocation, I have to define J as 64-bit, although it's physically 32-bit. This

Hi, > (4) llc -march=hexagon test.ll -o test.s > > '' is not a recognized processor for this target (ignoring processor) > 0 llc 0x08c2512b > Stack dump: > 0. Program arguments: llc -march=hexagon test.ll -o test.s > 1. Running pass 'Function Pass Manager' on module 'test.ll'. > 2. Running pass 'Hexagon DAG->DAG Pattern Instruction

Hi there, I run tinc with not ConnectTo, (and it can't tcp-connect to the relevant other tincd, because that tincd is behind a firewall --> that tincd usualy connects to my tincd). If I start that tincd alone (not connected at all) and do a ping some_other_ip, it gets a SIGBUS in route.c:207 in the function route_ipv4_unreachable at the line: hdr->ip_v = 4; This seems to be an

Hi, On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > On 7/3/2012 5:01 AM, Duncan Sands wrote: >> Hi, >> >>> (4) llc -march=hexagon test.ll -o test.s >>> >>> '' is not a recognized processor for this target (ignoring processor) >>> 0 llc 0x08c2512b >>> Stack dump: >>> 0. Program

On 03/02/2010, at 10:16 PM, Anton Korobeynikov wrote: > Hello, Nathan > >> I've put together some preliminary patches to add frontend support for the sparcv9-* subtarget (ie 64-bit SPARC), modelled on the corresponding x86-64 code - do these look reasonable for inclusion? This doesn't address the codegen side of things yet (isel falls over when trying to actually emit

Hi Sebastian, On 19/07/12 05:57, Sebastian Pop wrote: > On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: >> Hi, >> >> On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >>> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>>> Hi, >>>> >>>>> (4) llc -march=hexagon

On 7/3/2012 5:01 AM, Duncan Sands wrote: > Hi, > >> (4) llc -march=hexagon test.ll -o test.s >> >> '' is not a recognized processor for this target (ignoring processor) >> 0 llc 0x08c2512b >> Stack dump: >> 0. Program arguments: llc -march=hexagon test.ll -o test.s >> 1. Running pass 'Function Pass Manager' on module

openssh 3.7p1 sshd on Solaris 8 / sparcv9: sshd runs fine, and starts to allow the login. However, when reading from /etc/default/login, I get a bus error. I am able to get sshd to work by commenting out these lines in session.c: 1015,1018c1015 < # ifdef HAVE_ETC_DEFAULT_LOGIN < read_etc_default_login(&env, &envsize, pw->pw_uid); < path =

On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: > Hi, > > On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>> Hi, >>> >>>> (4) llc -march=hexagon test.ll -o test.s >>>> >>>> '' is not a recognized

Hi all, I've put together some preliminary patches to add frontend support for the sparcv9-* subtarget (ie 64-bit SPARC), modelled on the corresponding x86-64 code - do these look reasonable for inclusion? This doesn't address the codegen side of things yet (isel falls over when trying to actually emit 64-bit code), but at least bitcode generation looks correct now. Tested on

sorry, llc -march=hexagon -mcpu=hexagonv2 test.ll -o test.s works. 2012/7/3 Triple Yang <triple.yang at gmail.com>: > hi, > > does someone notice that llc options "-march=hexagon" and > "-march-sparcv9" do not work well under llvm 3.1? > > Following is a brief description: > (1) test.c file > > int cmp(int i, int j) { > return