similar to: [LLVMdev] Adding xadd instruction to X86

On Thu, 2 Dec 2004, Brent Monroe wrote: > I'm trying to add the xadd instruction to the X86 back end. > xadd r/m32, r32 > exchanges r/m32 and r32, and loads the sum into r/m32. I'm > interested in the case where the destination operand is a > memory location. > > I've added the following entry to X86InstrInfo.td: > def XADD32mr : I<0x87, MRMDestMem, >

Chris Lattner wrote: > On Thu, 2 Dec 2004, Brent Monroe wrote: > >>I'm trying to add the xadd instruction to the X86 back end. >>xadd r/m32, r32 >>exchanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to

On Mon, Feb 9, 2015 at 4:02 AM, Peter Zijlstra <peterz at infradead.org> wrote: > On Mon, Feb 09, 2015 at 03:04:22PM +0530, Raghavendra K T wrote: >> So we have 3 choices, >> 1. xadd >> 2. continue with current approach. >> 3. a read before unlock and also after that. > > For the truly paranoid we have probe_kernel_address(), suppose the lock > was in

On Mon, Feb 9, 2015 at 4:02 AM, Peter Zijlstra <peterz at infradead.org> wrote: > On Mon, Feb 09, 2015 at 03:04:22PM +0530, Raghavendra K T wrote: >> So we have 3 choices, >> 1. xadd >> 2. continue with current approach. >> 3. a read before unlock and also after that. > > For the truly paranoid we have probe_kernel_address(), suppose the lock > was in

On 02/10, Raghavendra K T wrote: > > On 02/10/2015 06:23 AM, Linus Torvalds wrote: > >> add_smp(&lock->tickets.head, TICKET_LOCK_INC); >> if (READ_ONCE(lock->tickets.tail) & TICKET_SLOWPATH_FLAG) .. >> >> into something like >> >> val = xadd((&lock->ticket.head_tail, TICKET_LOCK_INC << TICKET_SHIFT);

On 02/10, Raghavendra K T wrote: > > On 02/10/2015 06:23 AM, Linus Torvalds wrote: > >> add_smp(&lock->tickets.head, TICKET_LOCK_INC); >> if (READ_ONCE(lock->tickets.tail) & TICKET_SLOWPATH_FLAG) .. >> >> into something like >> >> val = xadd((&lock->ticket.head_tail, TICKET_LOCK_INC << TICKET_SHIFT);

Hi all, I want to match addition with 16bit integers. So I define a pattern fragment as follows: def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; Now I am confused between (add R32:$dst, simm16:$im) and (add R32:$dst, (i32 simm16:$im)). Do both of them match the same pattern? Are they equivalent? If not what is the difference? I am also confused as to how

On 02/09/2015 02:44 AM, Jeremy Fitzhardinge wrote: > On 02/06/2015 06:49 AM, Raghavendra K T wrote: [...] > >> Linus suggested that we should not do any writes to lock after unlock(), >> and we can move slowpath clearing to fastpath lock. > > Yep, that seems like a sound approach. Current approach seem to be working now. (though we could not avoid read). Related question:

On 02/09/2015 02:44 AM, Jeremy Fitzhardinge wrote: > On 02/06/2015 06:49 AM, Raghavendra K T wrote: [...] > >> Linus suggested that we should not do any writes to lock after unlock(), >> and we can move slowpath clearing to fastpath lock. > > Yep, that seems like a sound approach. Current approach seem to be working now. (though we could not avoid read). Related question:

Hello all, This new version (0.6.1) of asterisk-oh323 fixes the "one-way audio" problem of the previous release. Download from the usual location: http://www.inaccessnetworks.com/projects/asterisk-oh323 Regards, Michael.

* Greg KH <gregkh at linuxfoundation.org> wrote: > On Tue, Feb 24, 2015 at 02:54:59PM +0530, Raghavendra K T wrote: > > Paravirt spinlock clears slowpath flag after doing unlock. > > As explained by Linus currently it does: > > prev = *lock; > > add_smp(&lock->tickets.head, TICKET_LOCK_INC); > > > >

* Greg KH <gregkh at linuxfoundation.org> wrote: > On Tue, Feb 24, 2015 at 02:54:59PM +0530, Raghavendra K T wrote: > > Paravirt spinlock clears slowpath flag after doing unlock. > > As explained by Linus currently it does: > > prev = *lock; > > add_smp(&lock->tickets.head, TICKET_LOCK_INC); > > > >

Dear R helpers,   I have following input files. (Actually they are more than 10 rates but here i am considering only 2 rates to write my problem)   rate1.csv min1        max1            min2          max2          min3           max3 1.05        1.30               1.30          1.65             1.65          1.99   rate2.csv min1        max1            min2          max2          min3          

If I have an instruction which has many register and immediate operands, what's the difference between these two implementations to define the instruction in TableGen *.td file? (1) Similar to what has been done to complex X86 addressing mode. A single 32-bit immediate (i32) encodes how to add many MachineOperands to the MachineInstr object (With the help of functions in X86InstrBuilder.h).

Hello, consider the following IR code : %count4 = getelementptr inbounds %struct.r32, %struct.r32* %cur.087, i64 0, i32 4 How to check in the instruction, whether the operand is a structure or not if(isa<GetElementPtrInst>(instruction)) { GetElementPtrInst *getElementPtrInst=dyn_cast<GetElementPtrInst>(&instruction); //check if getElemetPtrInst operands structure or array. }

Paravirt spinlock clears slowpath flag after doing unlock. As explained by Linus currently it does: prev = *lock; add_smp(&lock->tickets.head, TICKET_LOCK_INC); /* add_smp() is a full mb() */ if (unlikely(lock->tickets.tail & TICKET_SLOWPATH_FLAG)) __ticket_unlock_slowpath(lock, prev); which is

Paravirt spinlock clears slowpath flag after doing unlock. As explained by Linus currently it does: prev = *lock; add_smp(&lock->tickets.head, TICKET_LOCK_INC); /* add_smp() is a full mb() */ if (unlikely(lock->tickets.tail & TICKET_SLOWPATH_FLAG)) __ticket_unlock_slowpath(lock, prev); which is

2005/7/24, Chris Lattner <sabre at nondot.org>: > Ah, ok. In that case, you want to put all of the registers in one register > file, and not make the constant register allocatable (e.g. see > X86RegisterInfo.td, and note how the register classes include EBP and ESP, > but do not register allocate them (through the definition of > allocation_order_end()). > > -Chris

Hi, say I have two register classes GR and AR, and a move instruction that can move one register to another, no matter what the class is. What's the best way to describe the operands DAG? If I just write (ops GR:$src, GR:$dst) this will cover 1/4 of all possible combinations, and writing 4 instructions variants is troublesome. Is there any syntax that write something: pseudo-class R32

I`m folowing the steps on the unofficial Samba how to. I already join my WinXP box to the domain but I can`t login from my WinXP box after restart. There is an error message that sais: Windows can`t connect to the domain because the domain controller is unable or I`m using Samba-2.2.7a on red hat 9.0 with kernel 2.4.20-18.9 this is my smb.conf [global] domain logons = yes