similar to: OPUS implementation with FPGA

Displaying 20 results from an estimated 1000 matches similar to: "OPUS implementation with FPGA"

2013 Oct 05
1
OPUS implementation with FPGA
Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the
2013 Oct 06
2
Encoder off by one
Why does opus_encode return 359, and not 360, please? This is my code: int iShortsRead = fread(m_RawBytes, sizeof(short), (5760/sizeof(short)), fin); for(int i=0;i<iShortsRead;i++) { opus_int32 s; s=m_RawBytes[2*i+1]<<8|m_RawBytes[2*i]; s=((s&0xFFFF)^0x8000)-0x8000; m_ShortsInput[i]=s; }
2013 Oct 06
1
Encoder off by one
If you encode with int iByteSizeEncoded = opus_encode(m_enc, m_ShortsInput, (1920/sizeof(short)), m_EncodedBytes, (960*6)); ... the byte size is 120. I thought that an odd value like 359 has to be a fault on my side. I thought it would be a multiple of something. So 359 is really correct??? Thank you for clearing this up. Am 06.10.2013 16:50, schrieb Jean-Marc Valin: > Why
2013 Nov 14
2
How to negotiate 'Opus/Celt only'?
Hi, Since our device can only handle the Celt part of Opus (due to a MIPS limitation), we have two questions: 1. Is it possible to via SDP force the remote party to send a specific mode of the 32 different possible modes or to force the remote side to use CELT only? 2. In the reference implementation of Opus it looks like the only way to force the encoder to use CELT only
2013 Oct 06
0
Encoder off by one
Why should it return 360 in the first place??? On 10/06/2013 06:33 AM, Hermann Weber wrote: > Why does opus_encode return 359, and not 360, please? > > This is my code: > > int iShortsRead = fread(m_RawBytes, sizeof(short), > (5760/sizeof(short)), fin); > for(int i=0;i<iShortsRead;i++) > { > opus_int32 s; >
2013 Oct 05
0
OPUS implementation with FPGA
I'm not aware of an FPGA implementations yet. You could be the first! An encoder implementation would be much easier, because there are almost no rules about encoders. An encoder is free to behave any way it wants, so you could implement a very small subset of Opus and still have a compliant (and useful) encoder. A decoder implementation would be much harder, because decoders are required
2011 Aug 22
1
[LLVMdev] llvm-fpga microblaze target
folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.
2004 Sep 07
3
FPGA implementation in the camera
I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.
2004 Sep 07
3
FPGA implementation in the camera
I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.
2004 Nov 17
4
FPGA implementation
Andrey Fillipov posted the following update at his sourceforge website on 11/16/04. "Coded and simulated the DC predictor module - hope the Theora description I used matches the actual codec :-) Also modified the modules released earlier to support non-coded blocks. For the DCT/IDCT I tried to reduce the power consuption by minimizing switching of the registers and counters when the
2008 Sep 03
1
[LLVMdev] LLVM FPGA interface.
Hi LLVM community members. I downloaded LLVM-GCC4.2 Front-end source code and succefully installed alongwith LLVM-2.3 on linux x86_64. I think it's front-end has better optimizations. I am naive to LLVM environment, my focus is to generate LLVM inermediate code for FPGA. Are there any resources/links/papers/documents which discusses LLVM intermediate generation for FPGA needs. I am aware
2007 May 07
2
Theora running on FPGA
Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled
2011 Aug 20
2
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
i was just writing this: http://www.gp32x.com/board/index.php?/topic/60228-replicating-the-success-of-the-openpandora-discussion-v20/ when something that just occurred to me, half way through, and i would greatly appreciate some help evaluating whether it's feasible. put these together: http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm
2011 Mar 22
5
FPGA encode stages flow diagram
Good day! I create diagram of encoder process. Using it i create implementation of encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing stages? Here is blog http://developer-fpga.blogspot.com/ Here is picture of encoding stage 1 https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg Here is picture of encoding stage 2
2011 Aug 20
0
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
Luke Kenneth Casson Leighton wrote: > i was just writing this: > http://www.gp32x.com/board/index.php?/topic/60228-replicating-the-success-of-the-openpandora-discussion-v20/ > > when something that just occurred to me, half way through, and i would > greatly appreciate some help evaluating whether it's feasible. > > put these together: >
2011 Aug 21
4
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky <nicholas at mxc.ca> wrote: > The way in which Gallium3D targets LLVM, is that it waits until it receives > the shader program from the application, then compiles that down to LLVM IR. > That's too late to start synthesizing hardware (unless you're planning to > ship an FPGA as the graphics card, in which case reprogramming
2007 Aug 25
1
Theora playing on a FPGA
Hi all, Great news. On Thursday I finally play a video on FPGA. As I said the implementation is using the NIOS II processor. Andr? Costa is hard working to use the LEON processor. The video resolution is 96x80, because we have some FPGA internal memory constraints. I will try to use external memory to make possible decode a video of at least 320x240. The result can be see here:
2011 Aug 21
0
[LLVMdev] Xilinx zynq-7000 (7030) as a Gallium3D LLVM FPGA target
Luke Kenneth Casson Leighton wrote: > On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky<nicholas at mxc.ca> wrote: > >> The way in which Gallium3D targets LLVM, is that it waits until it receives >> the shader program from the application, then compiles that down to LLVM IR. >> That's too late to start synthesizing hardware (unless you're planning to >>
2006 Dec 20
1
SVN Theora FPGA
Hi, I did some improvements and some bug corrections in Theora FPGA code. I'd like to post this new version in the SVN. How can I do that? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956
2003 Oct 03
2
Ascom Ascotel 2050 & Fritz PCI Card (Capi)
Hello, We have been trying to add asterisk to our Ascom Ascotel 2050 PBX. We have a AVM Fritz!PCI Card connected to an S0 bus extension from the PBX. The fritz card is configured to use chan_capi, and we can make calls SIP->SIP SIP->PBX extension PBX extension->SIP all successfully, we have assigned more than one PBX extension number to the S0 port in the Ascom PBX (it has 8 positions)