similar to: [PATCH 0/11] Add suspend/resume support for GK20A

On Tue, Jan 06, 2015 at 05:34:01PM +0800, Vince Hsu wrote: > > On 01/05/2015 11:25 PM, Thierry Reding wrote: > >* PGP Signed by an unknown key > > > >On Thu, Dec 25, 2014 at 10:42:58AM +0800, Vince Hsu wrote: > >>On 12/24/2014 09:23 PM, Lucas Stach wrote: > >>>Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>>>This patch

On Tue, Jan 06, 2015 at 08:13:01PM +0800, Vince Hsu wrote: > > On 01/06/2015 07:36 PM, Thierry Reding wrote: > >* PGP Signed by an unknown key > > > >On Tue, Jan 06, 2015 at 05:34:01PM +0800, Vince Hsu wrote: > >>On 01/05/2015 11:25 PM, Thierry Reding wrote: > >>>>Old Signed by an unknown key > >>>On Thu, Dec 25, 2014 at 10:42:58AM

On Thu, Dec 25, 2014 at 10:42:58AM +0800, Vince Hsu wrote: > > On 12/24/2014 09:23 PM, Lucas Stach wrote: > >Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>This patch adds some missing pieces of the rail gaing/ungating sequence that > >>can improve the stability in theory. > >> > >>Signed-off-by: Vince Hsu <vinceh at

Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > This patch adds some missing pieces of the rail gaing/ungating sequence that > can improve the stability in theory. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drm/nouveau_platform.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > drm/nouveau_platform.h | 3 +++ > 2 files changed, 45

On Tue, Dec 23, 2014 at 06:39:56PM +0800, Vince Hsu wrote: > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drivers/memory/tegra/tegra124.c | 82 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c > index 278d40b854c1..036935743a0a 100644 > ---

On Tue, Jan 06, 2015 at 11:07:45PM +0800, Vince Hsu wrote: > On 03:30:00PM Jan 06, Thierry Reding wrote: > > * PGP Signed by an unknown key > > > > On Tue, Dec 23, 2014 at 06:39:56PM +0800, Vince Hsu wrote: > > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > > > --- > > > drivers/memory/tegra/tegra124.c | 82

On Tue, Dec 23, 2014 at 06:39:55PM +0800, Vince Hsu wrote: > The flush operation of memory clients is needed for various IP blocks in > the Tegra SoCs to perform a clean reset. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drivers/memory/tegra/mc.c | 21 +++++++++++++++++++++ > include/soc/tegra/mc.h | 23 ++++++++++++++++++++++- > 2 files changed,

This patch series is the final (?) step towards the initial support of GK20A, allowing it to be probed and used (currently at a very slow speed, and for offscreen rendering only) on the Jetson TK1 and Venice 2 boards. The main piece if the first patch which adds platform devices probing support to Nouveau. There are probably lots of things that need to be discussed about it, e.g.: * The way the

This series adds support for probing platform devices on Nouveau, as well as the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since a few extra things need to be supported before that. This version is mostly identical to v2 but fixes an important issue: the drvdata must be set to the drm_device for sysfs to work, so the platform device structure now includes the

This series adds support for probing platform devices on Nouveau, as well as the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since a few extra things need to be supported before that. Thanks to the input received for v1, this version is more self-contained and shares less stuff between nouveau_drm and nouveau_platform. The major change is that nouveau_platform is now

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > The Tegra124 and later Tegra SoCs have a sepatate rail gating register > to enable/disable the clamp. The original function > tegra_powergate_remove_clamping() is not sufficient for the enable > function. So add a new function which is dedicated to the GPU rail > gating. Also don't refer to the powergate ID since the

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

Hi, Generally the the imported buffers which has memory type TTM_PL_TT are mapped as small pages probably due to lack of big page allocation. But the platform device which also use memory type TTM_PL_TT, like GK20A, can *allocate* big page though the IOMMU hardware inside the SoC. This is a try to map the imported buffers as big pages in GMMU by the platform IOMMU. With some preparation work to

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

On 04:12:54PM Jan 07, Peter De Schrijver wrote: > On Wed, Jan 07, 2015 at 06:49:27PM +0800, Vince Hsu wrote: > > > > On 01/07/2015 06:19 PM, Peter De Schrijver wrote: > > >On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote: > > >>* PGP Signed by an unknown key > > >> > > >>On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu

On 01/06/2015 07:36 PM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Jan 06, 2015 at 05:34:01PM +0800, Vince Hsu wrote: >> On 01/05/2015 11:25 PM, Thierry Reding wrote: >>>> Old Signed by an unknown key >>> On Thu, Dec 25, 2014 at 10:42:58AM +0800, Vince Hsu wrote: >>>> On 12/24/2014 09:23 PM, Lucas Stach wrote:

Am Donnerstag, den 25.12.2014, 10:28 +0800 schrieb Vince Hsu: > On 12/24/2014 09:16 PM, Lucas Stach wrote: > > Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >> The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >> to enable/disable the clamp. The original function > >> tegra_powergate_remove_clamping() is not sufficient for

On 02:55:52PM Jan 06, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Jan 06, 2015 at 08:13:01PM +0800, Vince Hsu wrote: > > > > On 01/06/2015 07:36 PM, Thierry Reding wrote: > > >> Old Signed by an unknown key > > > > > >On Tue, Jan 06, 2015 at 05:34:01PM +0800, Vince Hsu wrote: > > >>On 01/05/2015 11:25 PM,