similar to: [PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved

Displaying 20 results from an estimated 400 matches similar to: "[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved"

2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index f010767..4a9e48f 100644 ---
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
Unfortuantely we don't know if a particular load is a real 2d image (as would be a cube face or 2d array element), or a layer of a 3d image. Since we pass in the TIC reference, the instruction's type has to match what's in the TIC (experimentally). In order to properly support bindless images, this also can't be done by looking at the current bindings and generating appropriate
2014 Jan 13
20
[PATCH 00/19] nv50: add sampler2DMS/GP support to get OpenGL 3.2
OK, so there's a bunch of stuff in here. The geometry stuff is based on the work started by Bryan Cain and Christoph Bumiller. Patches 01-12: Add support for geometry shaders and fix related issues Patches 13-14: Make it possible for fb clears to operate on texture attachments with an explicit layer set (as is allowed in gl 3.2). Patches 15-17: Make ARB_texture_multisample work
2017 Dec 20
2
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
This is parallel to the pre-SM50 change which does this. Adjusts the shuffles / quadops to make the values correct relative to lane 0, and then splat the results to all lanes for the final move into the target register. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Entirely untested beyond compilation. Should check bin/tex-miplevel-selection textureGrad Cube
2014 Jul 05
0
[PATCH] nvc0: do quadops on the right texture coordinates for TXD
handleTEX moves the layer as the first argument. This makes sure that the quadops deal with the texture coordinates. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git
2014 Jul 05
1
[PATCH 1/2] nv50/ir: retrieve shadow compare from first arg
This can only happen with texture(samplerCubeShadow, bias), where the compare will be in the first argument. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git
2015 Feb 23
2
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
Does this give correct results for special floats (0, infs)? We tried to improve (for single floats) x86 rcp in llvmpipe with newton-raphson, but unfortunately not being able to give correct results for these two cases (without even more additional code) meant it got all disabled in the end (you can still see that code in the driver) since the problems are at least as bad as those due to bad
2014 Feb 04
1
[PATCH] nouveau/codegen: allow tex offsets on non-TXF instructions (e.g. TXL)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- This fixes the bin/fs-textureOffset-2D piglit test on nv50. Have yet to re-run the full piglit suite with this change in place, but it seems pretty obvious. src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Untested beyond compiling a few shaders to see if they look like they might work. nvdisasm agrees with envydis's decoding of these things. Will definitely get ahold of a G200 to run tests on before pushing this. .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 94 ++++++++++++++++++---
2017 Aug 12
3
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
On using builtin functions we have to move the input to registers $0 and $1, if one of the input value is an immediate, we fail to propagate the immediate: ... mov u32 $r477 0x00000003 (0) ... mov u32 $r0 %r473 (0) mov u32 $r1 $r477 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... With this patch the immediate is propagated, potentially causing the first MOV to be superfluous, which we'd
2018 Sep 11
1
Questions on Maxwell/Pascal Texture Instructions Modes
Hello, I got some doubts on how texture modes work on TEX, TEXS, TLD4, etc instructions. I got: DC, AOFFI, NDV, NODEP, MZ, PTP modes as well as LZ Mode. How does this work or change the behavior of the texture instruction. So far of those I know AOFFI defines an Offset but I'm on blanks for the rest. -------------- next part -------------- An HTML attachment was scrubbed... URL:
2014 Apr 04
2
[PATCH 1/2] nvc0: add support for texture gather
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Tested on NVE6. Very strange that it seems to use 8 bits for offsets, vs 4 bits used by texelFetch. But this passes the piglit tests. Will test on a NVCX before checking in, in case it's different there. (Although that'd be surprising, given the similarities between the 2 ISAs.)
2006 Oct 02
1
Problems Deploying a Camping app on TxD
So I''ve been trying all day to get a small camping app I wrote up on Textdrive to no avail. Right now I''m getting a 500 error when I go to the site, and it spits this out (from lightty after i restart it and make a request to the app): (eval):13:in `initialize'': undefined method `to_hash'' for #<FCGI::Stream:0x83a35d8> (NoMethodError) from
2017 Aug 13
1
[PATCH v2] nvc0/ir: propagate immediates to CALL input MOVs
On using builtin functions we have to move the input to registers $0 and $1, if one of the input value is an immediate, we fail to propagate the immediate: ... mov u32 $r477 0x00000003 (0) ... mov u32 $r0 %r473 (0) mov u32 $r1 $r477 (0) call abs BUILTIN:0 (0) mov u32 %r495 $r1 (0) ... With this patch the immediate is propagated, potentially causing the first MOV to be superfluous, which we'd
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.3" <mesa-stable at lists.freedesktop.org> --- With this, all the tex-miplevel-selection tests pass on maxwell. There is a minor bit of this change which affects textureGrad on kepler that I have yet to test, but I'm moderately sure it's correct and was only working by luck before. (Changing the insbf to use
2016 May 14
1
[Bug 95403] New: [GK110] misaligned_gpr spamming dmesg when playing victor vran
https://bugs.freedesktop.org/show_bug.cgi?id=95403 Bug ID: 95403 Summary: [GK110] misaligned_gpr spamming dmesg when playing victor vran Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: minor Priority: medium Component:
2015 Nov 16
2
Contact-closure UPS
Hello, I have one UPS Infosec XP Pro 2500 RM and it works with windows sw RUPS2000. Now I want to install this UPS as virtual server on vmware ESXi vMA - (SUSE SLES 11SP2 linux). On this linux I have NUT 2.6.0 and I stopped now with configuration of genericups driver. Working cable (direct cable pin1-pin1 ... pin9-pin9) connection on Windows: PIN | PC | UPS
2006 Jun 09
1
SBC/ATT Supertrunk configuration
I have what my SBC/ATT representative calls a "Supertrunk," but he can't tell me the specifics I need to know to configure Asterisk to work with it. By fiddling about, I've come up with the "almost working" configuration below. This works except that it takes about 4 seconds from when the console says the line is answered until it plays my prompt. Watching the
2005 Jun 08
7
Rails/lighttpd: Changes to controller not being seen?
This is a weird one: My app works fine on our local box with webrick. After uploading to TxD server, the app starts behaving weirdly. I make some edits to one of the controllers and my changes don''t seem to be going through. So I go ahead and change the name of the controller file. The page loads without error. I figure maybe I''m in the wrong directory, so I change the
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index dfb093c..e38a3b8 100644 ---