similar to: [Bug 80738] New: Possible wrong variable used in nouveau_allocate_surface

--- src/nouveau_dri2.c | 4 +++- src/nv_accel_common.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/nouveau_dri2.c b/src/nouveau_dri2.c index d14443f..b99893f 100644 --- a/src/nouveau_dri2.c +++ b/src/nouveau_dri2.c @@ -46,6 +46,8 @@ nouveau_dri2_create_buffer(DrawablePtr pDraw, unsigned int attachment, ppix->refcnt++; } else { + /*

With this patch the DDX almost works with GK20A, the missing piece is adding COHERENT mappings to the right places. ;-) If you specify NOUVEAU_BO_APER the kernel will truncate valid_domains to the domains specified at creation time. This means that as long as we only specify the correct domain in nouveau_allocate_surface the effect is still the same. Signed-off-by: Maarten Lankhorst <dev at

For now pixmaps will only be tiled if driver pixmaps are being used and we're told to with the NOUVEAU_CREATE_PIXMAP_TILED usage hint. Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- src/nouveau_exa.c | 31 ++++++++++++++++++++----------- src/nv50_exa.c | 6 +++--- src/nv50_xv.c | 2 +- src/nv_proto.h | 2 +- src/nv_type.h | 1 + 5 files

Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com> --- src/nv_accel_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/nv_accel_common.c b/src/nv_accel_common.c index 4484c1c..eebb0ab 100644 --- a/src/nv_accel_common.c +++ b/src/nv_accel_common.c @@ -37,7 +37,7 @@ nouveau_allocate_surface(ScrnInfoPtr scrn, int width, int height, int bpp, Bool tiled =

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Untested. src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 3 +++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 14 insertions(+) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index 7118a7a..7fbcc87 100644 --- a/src/nouveau_copy.c

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- v1 -> v2: add 0x130 as a valid chip type early on in detection src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 4 ++++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 15 insertions(+) diff --git a/src/nouveau_copy.c

Allow setting the block layout of a nouveau FB object using DRM format modifiers. When specified, the format modifier block layout and kind overrides the GEM buffer's implicit layout and kind. The specified format modifier is validated against he list of modifiers supported by the target display hardware. Signed-off-by: James Jones <jajones at nvidia.com> ---

On 12/11/19 1:13 PM, Ilia Mirkin wrote: > On Wed, Dec 11, 2019 at 4:04 PM James Jones <jajones at nvidia.com> wrote: >> >> Allow setting the block layout of a nouveau FB >> object using DRM format modifiers. When >> specified, the format modifier block layout and >> kind overrides the GEM buffer's implicit layout >> and kind. The specified format

Do not attach fences automatically to buffers that are marked for explicit synchronization. Signed-off-by: Lauri Peltonen <lpeltonen at nvidia.com> --- drm/nouveau_bo.c | 8 ++++---- drm/nouveau_bo.h | 4 ++-- drm/nouveau_drm.c | 1 + drm/nouveau_gem.c | 47 +++++++++++++++++++++++++++++++++++++++------- drm/nouveau_gem.h | 6 ++++--

From: Maarten Lankhorst <maarten.lankhorst at canonical.com> Make sure that buffers are always aligned. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 40 +++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c

On Wed, Dec 11, 2019 at 4:04 PM James Jones <jajones at nvidia.com> wrote: > > Allow setting the block layout of a nouveau FB > object using DRM format modifiers. When > specified, the format modifier block layout and > kind overrides the GEM buffer's implicit layout > and kind. The specified format modifier is > validated against he list of modifiers supported

On Tue, 17 Dec 2019 at 10:45, James Jones <jajones at nvidia.com> wrote: > > Make sure framebuffer dimensions and tiling > parameters will not result in accesses beyond the > end of the GEM buffer they are bound to. > > Signed-off-by: James Jones <jajones at nvidia.com> > --- > drivers/gpu/drm/nouveau/nouveau_display.c | 93 +++++++++++++++++++++++ > 1 file

Make sure framebuffer dimensions and tiling parameters will not result in accesses beyond the end of the GEM buffer they are bound to. Signed-off-by: James Jones <jajones at nvidia.com> --- drivers/gpu/drm/nouveau/nouveau_display.c | 93 +++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c

On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote: > On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding <thierry.reding at gmail.com> wrote: > > > > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote: > > > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann <kraxel at redhat.com> wrote: > > > > > > > > Hi, > > > >

This flips GM10x to using the updated format, which is what I tested with. However GM20x and GP10x also use this TIC format. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nvc0_accel.c | 11 ++++++++++ src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ src/nvc0_exa.c | 22 ++++--------------- src/nvc0_xv.c | 67

This flips GM10x to using the updated format, which is what I tested with. However GM20x and GP10x also use this TIC format. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nvc0_accel.c | 11 ++++++++++ src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ src/nvc0_exa.c | 23 ++++--------------- src/nvc0_xv.c | 67

On Mon, Oct 17, 2016 at 5:46 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Few comments below. > > On 10/16/2016 09:14 PM, Ilia Mirkin wrote: >> >> This flips GM10x to using the updated format, which is what I tested >> with. However GM20x and GP10x also use this TIC format. >> >> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

On Thu, Oct 27, 2016 at 1:19 PM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Are you sure this refactoring doesn't break anything? > > Few comments inline. > > > On 10/27/2016 04:02 PM, Ilia Mirkin wrote: >> >> This flips GM10x to using the updated format, which is what I tested >> with. However GM20x and GP10x also use this TIC format.

On Fri, Jul 17, 2020 at 11:57:57AM -0700, James Jones wrote: > Accept the DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK() > family of modifiers to handle broken userspace > Xorg modesetting and Mesa drivers. > > Tested with Xorg 1.20 modesetting driver, > weston at c46c70dac84a4b3030cd05b380f9f410536690fc, > gnome & KDE wayland desktops from Ubuntu 18.04, > and sway 1.5 Just

Are you sure this refactoring doesn't break anything? Few comments inline. On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h |