similar to: [PATCH] nouveau/drm/fifo: fix ENG_RUNLIST register address

Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/engine/fifo/gf100.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/fifo/gf100.c

Memory was always allocated for 4096 channels. Change this to allocate what we actually need according to the number of channels we use. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

The patches contain some tidy-up work, and refactoring that has arisen as a by-product of my initial work on adding TV support to nv50. Joel Holdsworth (4): drm/nouveau: Removed unneeded include in nvc0_fence.c drm/nouveau: Replaced magic numbers with defines from nouveau_reg drm/nouveau: Replaced copy-pasted nv_wait with nv50_wait_dpms_ctrl helper drm/nouveau: Refactored encoder

--- drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c index 61e29d6..98bded6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c @@ -33,6

--- drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c | 27 +++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c index b36addf..61e29d6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c @@

Resend of patch #7 to fix behaviour when failing to pause parts of the GPU

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- .../gpu/drm/nouveau/core/include/subdev/clock.h | 3 ++ drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | 45 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c | 30 ++++----------- 3 files changed, 55 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h

Re-resend of patch #7 to move the _post and _pre function prototypes to nva3.h

V2: always call post correctly even if pre fails Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- .../gpu/drm/nouveau/core/include/subdev/clock.h | 3 ++ drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | 52 +++++++++++++++++++++- drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c | 36 +++++---------- 3 files changed, 66 insertions(+), 25 deletions(-) diff --git

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated

Here are a few small fixes for issues we found while implementing support for GM20B. The first two are specific to Tegra/GK20A, but the last 3 patches may have a broader (hopefully beneficial) effect. Note that the newly introduced gf100_gr_wait_idle() function on patch 5/5 is exported on purpose. GK20A and GM20B drivers will soon make use of it. Ben, since you seemed to like these changes, a

A naive question from someone who knows nothing of icmd or bundles... Would it be better to wait for both bits to become 0 (I.e. 0x6)? On Jun 8, 2015 11:54 AM, "Alexandre Courbot" <acourbot at nvidia.com> wrote: > When emitting the ICMD bundle, wait on the bottom half (bit 3 of the > GR_STATUS register) instead of upper half (bit 2) to make sure methods > are effectively

On Wed, Apr 2, 2014 at 9:52 AM, Alexandre Courbot <gnurou at gmail.com> wrote: > On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding > <thierry.reding at gmail.com> wrote: >> On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote: >> [...] >>> diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c

v2: Check for PFIFO, don't pause if it's not yet running. This should fix reclocking on boot Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 4 +- .../gpu/drm/nouveau/core/include/subdev/clock.h | 4 + drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c | 439

v2: Check for PFIFO, don't pause if it's not yet running. This should fix reclocking on boot v3: Tiny clean up Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 4 +- .../gpu/drm/nouveau/core/include/subdev/clock.h | 4 +

This reverts commit 1addc1264852 This commit seems to cause crashes in gk104_fifo_intr_runlist() by returning 0xbad0da00 when register 0x2a00 is read. Since this commit was intended for GM20B which is not completely supported yet, let's revert it for the time being. Reported-by: Eric Biggers <ebiggers3 at gmail.com> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> ---

Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to

On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote: [...] > diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c [...] > +#include <subdev/ibus.h> > + > +struct nvea_ibus_priv { > + struct nouveau_ibus base; > +}; > + > +static void > +nvea_ibus_init_priv_ring(struct nvea_ibus_priv *priv) >

https://bugs.freedesktop.org/show_bug.cgi?id=37669 Summary: [NVAC] problem when disabling external monitor Product: xorg Version: unspecified Platform: Other OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org

The patches contain some tidy-up work, and refactoring that has arisen as a by-product of my initial work on adding TV support to nv50. Best Regards Joel Holdsworth -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-drm-nouveau-Removed-unneeded-include-in-nvc0_fence.c.patch Type: text/x-patch Size: 726 bytes Desc: not available URL: