similar to: Proposal for a LLVM front-end for P4 language

> On Oct 10, 2016, at 2:50 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > > From: "Dangeti Tharun kumar via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > To: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > Cc: "Santanu Das" <cs15mtech11018 at iith.ac.in <mailto:cs15mtech11018 at

Dear community, Our team at IITH have been experimenting with loop-distribution pass in LLVM. We see the following results on few benchmarks. clang -O3 -mllvm -enable-loop-distribute -Rpass=loop-distribute file.c clang -O3 -mllvm -enable-loop-distribute -Rpass-analysis=loop-distribute file.c TORCH

Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; llvm-dev at lists.llvm.org Subject: [EXT] Re:

On Mon, Jan 7, 2019 at 3:21 PM Dean Michael Berris <dean.berris at gmail.com> wrote: > On Mon, Jan 7, 2019 at 8:43 PM Dangeti Tharun kumar > <cs15mtech11002 at iith.ac.in> wrote: > > > > Hi Dean, > > > > I have tried with -instr-map-1 and -instr-map-2, it didn't work. > > > > Yeah, I'm looking through the code and it looks like

Hi On Tue, Oct 30, 2018 at 10:47 PM Matthias Braun <mbraun at apple.com> wrote: > At a first glance I see nothing obviously wrong with the assembly, but it > is a big file. So if you have a specific part in mind, please copy into the > E-Mail discussion. > > I assume you are compiling for a mac or linux system? In that case none of > the xmm registers are callee saved (as

Hi, Gerolf. We've been a bit quiet for some time. After listening to feedback on the project internally and externally, we decided to take a more generally accepted community development model ---- building up through a collection of small incremental changes ---- than trying to make a big step forward. That change of course took a bit of time, but we are getting close to the first NFC patch

Hi Dangeti, Ramakrishna, Adam, and Gerolf, >Yes this is an area that needs further improvement. We have some immediate plans to make these more useful. See the recent llvm-dev threads [1], [2]. It takes a lot of dedicated effort to make vectorization report easier to understand by ordinary programmers (i.e., those who are not compiler writers). Having done that for ICC ourselves, we truly

Dear LLVM Community, I am D Tharun Kumar, masters student at Indian Institute of Technology Hyderabad, working in a team to improve current vectorizer in LLVM. As an initial study, we are studying various benchmarks to analyze and compare vectorizing capabilities of LLVM, GCC and ICC. We found that vectorization remarks given by LLVM are vague and brief, comparatively GCC and ICC are giving

Hi Dean, I have tried with -instr-map-1 and -instr-map-2, it didn't work. Is there a way to find the function name from the identifier? -DTharun On Mon, Jan 7, 2019 at 2:29 PM Dean Michael Berris <dean.berris at gmail.com> wrote: > Hi Dangeti, > > That's interesting -- can you try providing both `-instr-map-1=` and > `-instr-map-2=` even though they're the same

On Fri, Nov 2, 2018 at 3:31 PM Anton Korobeynikov <anton at korobeynikov.info> wrote: > > Yes, I am compiling for linux system. > > So the RA will not consider assigning a scratch register to a live range > crossing function call, though it may reduce spills? > Well, it has to spill the register – otherwise it could be clobbered by a > call. May be, I haven't

Hello, I read an interesting article on 2cpu.com that talks about the performance differences between a P4 processor with Hyperthreading(HT) enabled and disabled. http://www.2cpu.com/articles/ht_explored/index.html The bottom line of the article is that processor intensive applications greatly benefit from HT being enabled, but memory intensive applications can actually see a slight decrease in

Hi, In "target-features" list in LLVM-IR, there are "+feature", "-feature". My question is, does "-feature" is equivalent to not specifying a feature at all? For example: *attributes #0 = { "target-cpu"="znver2" "target-features"="+avx -avx2" }* Wheather it is equalent to omitting the avx2 from list? *attributes #0

vecremainder/novecremainder: Should the pragma simply call the vectorizer to attempt to vectorize the remainder loop, or should the vectorizer use a different method? > > Something like that. There were patches posted at some point to enable tail-loop vectorization. At this point, I imagine that you'd construct a VPlan with the vectorized tail. Yep, committed in

Hello, I have studied register allocation in theoretical aspects and exploring the same in the implementation level. I need a minimal testcase for register spilling to analyze spilling procedure in llvm. I tried with a testcase taking 20 variables but all the 20 variables are getting stored in the stack using %rbp. Maybe my live variable analysis is wrong. Please help me with a minimal testcase

On 8/8/19 2:03 PM, Hal Finkel wrote: Hi, First, as a high-level note, you posted a link to a Google doc, and at the end of the Google doc, you have a list of questions that you'd like answered. In the future, please put the questions directly in the email. For one thing, more people will read your email than will open your Google doc. Second, having the questions in the email should allow a

> There is a fundamental problem with the way that ivdep is defined by Intel's current documentation, at least for C/C++. As you note in your Google doc, it essentially says that the optimizer may ignore loop-carried dependencies except for those dependencies it can definitely prove are present. These are not semantics that any other compiler can actually replicate, and is not equivalent to

sir, I am able to generate .bc file for other normal code but my problem how to run the pass source code. If I write some pass then how should I run that pass? so please if you can help me in this and thanks for your reply. On Thu, Jun 5, 2014 at 11:34 AM, Alexander Musman < alexander.musman at gmail.com> wrote: > You are trying to use the pass source code to generate .bc file, it

Hi I have been facing a strange connectivity problem from CentOS and Fedora boxes. When I telnet to $ telnet adp.eease.com 443 it works fine some times and every 5-10 tries or so it says connection refused. And this does not happen from my windows box. Can anyone from this list try this on their linux installation and see if they get the same behaviour? Thanks Tharun

Greetings, (I am reposting this email of mine, as I was informed that emails from the domain 'iith.ac.in' are sometimes being marked as spam) I am Aradhya Biswas, final year student of Computer Science and Engineering at Indian Institute of technology Hyderabad (IITH), and as mentioned in my previous email on the LLVM dev mailing list, I am interested to work towards the improvement of

The Loop Optimization Working Group had a survey about “canonical” loop required by each loop transformation or analysis. That is, what should we normalize a loop before running a certain loop pass. Here is the survey result: https://tinyurl.com/rhuzny2 (Note that there are two workspaces: “By precondition” and “Breakdown”) Best - Min > On Dec 22, 2019, at 2:40 AM, Shraiysh Vaishay via