similar to: xtensa backend

Hello, I'm from Espressif Systems company, software department. Our company develops processors based on Xtensa architecture like ESP32 and ESP8266. We propose the integration of a backend targeting Xtensa architecture. We started to develop LLVM Xtensa backend almost a year ago. The reason was that we saw a demand from our large developers community. Currently only GNU compiler supports

Hello, James, Thank you very much for your advices! The next step in compiler development on Espressif is object file generation. There are no essential problems with this step, it will be implemented in nearest future. Currently Xtensa backend is able to print and parse assembly, I used about 1300 tests from gcc torture testsuite and GNU binutils to debug assembly output and now all tests

The current logic is wrong since we send fw->size >> 8 to the card. Rounding the size up by 0x100 and 0x1000 didn't seem to help, the card still hung, so go back to what the blob does -- 0x40000. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- What's currently in the tree causes the card to hang. Looking back at all the patches I sent, I always had the firmware

Hi, I am trying to build asterisk with xtensa compiler on embedded platform. I am trying to integrate my driver code to asterisk. For this tying to call driver code IOCTLs from chan_dahdi instead of dahdi IOCTLs. While compiling asterisk with xtensa, Observed chan_dahdi is not compiling [chan_dahdi.so is not creating].But with default settings [/usrc/src] it was creating. Please let me

Hey, Op 04-06-13 20:38, Ilia Mirkin schreef: > On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: >> These chipsets include the VP2 engine which is composed of a bitstream >> processor (BSP) that decodes H.264 and a video processor (VP) which can >> do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are >> driven by separate

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

This patchset centralizes the firmware-loading procedure to one set of functions instead of having each engine load its firmware as it pleases. This helps ensure that all firmware comes from the same place, namely nvidia/<chip>/. This changes where the firmware is fetched from for falcon/xtensa/bios, but these locations never seemed to have been official anyway. Also for most (all?) chips

Chris, this is a patch against top-of-tree. Maybe I wrote something wrong in the patch? $ svn info … Last Changed Author: chapuni Last Changed Rev: 203523 Last Changed Date: 2014-03-10 17:34:38 -0700 (Mon, 10 Mar 2014) $ svn diff Index: lib/IR/Verifier.cpp =================================================================== --- lib/IR/Verifier.cpp (revision 203523) +++ lib/IR/Verifier.cpp

In the following IR module: – define i8 @foo() #0 { entry: %call0 = call i8 @bar() ret i8 %call0 } declare i8 @bar() #1 – @bar() gets marked as its own user in top-of-tree LLVM. I patched the Verifier to check it (but didn’t commit the patch): – Index: lib/IR/Verifier.cpp =================================================================== --- lib/IR/Verifier.cpp (revision 203468) +++

No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield in sched.h. Suggested-by: Russell King <linux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h

No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield in sched.h. Suggested-by: Russell King <linux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

The following changes since commit afd2ff9b7e1b367172f18ba7f693dfb62bdcb2dc: Linux 4.4 (2016-01-10 15:01:32 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git tags/for_linus for you to fetch changes up to 43e361f23c49dbddf74f56ddf6cdd85c5dbff6da: checkpatch: add virt barriers (2016-01-12 20:47:08 +0200)

The following changes since commit afd2ff9b7e1b367172f18ba7f693dfb62bdcb2dc: Linux 4.4 (2016-01-10 15:01:32 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git tags/for_linus for you to fetch changes up to 43e361f23c49dbddf74f56ddf6cdd85c5dbff6da: checkpatch: add virt barriers (2016-01-12 20:47:08 +0200)

On 11/19/2013 08:16 PM, Ilia Mirkin wrote: > Hello, > > I hope this is an appropriate style of request for this forum. I added > code to support video decoding on the tesla cards that have a > similar-style video decoding engine to fermi cards (i.e. G98, GT21x, > the IGP's -- the falcon-controlled decoding engines, rather than the > xtensa-controlled ones), by using

Hello If I optimize (opt -std-compile-opts ) the following .ll ; ModuleID = 'call0.ll' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i386-mingw32" define i32 @t(i32 %a) nounwind { entry: %0 = tail call i32 inttoptr (i32 0 to i32 (i32)*)(i32 %a) nounwind

Hi All, I have gone through threads related to throughput issue in this list. Found few similar issue, but could not get the solution. So looking for some advice from group. I am trying to use the samba to access a USB disk connected to our evaluation board which has xtensa core running at 400 MHz. Samba 3.5.x is running on the board. We are getting below throughput as tested with the

Hello, I don't have advanced on the NHW Project this past month, but I have definitely validated its characteristics and this new version. The NHW Codec preserves or enhances image neatness and sharpness, which translates that on good quality images the NHW Codec is globally better than HEVC, and on degraded (with blur, artifacts) images it is worse than HEVC because it lacks of precision. I

llc accepts all the -debug variants when built with asserts (or debug build). It will accept -debug as well as -debug=prologepilog for your case. On Wed, Mar 21, 2018 at 7:27 AM, Meet Udeshi via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I want to check debug output of "PrologEpilogInserter" machine pass, and I > have seen in the code that there are various `DEBUG`

On Wed, Jun 5, 2013 at 3:05 AM, Maarten Lankhorst <maarten.lankhorst at canonical.com> wrote: > Hey, > > Op 04-06-13 20:38, Ilia Mirkin schreef: >> On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: >>> These chipsets include the VP2 engine which is composed of a bitstream >>> processor (BSP) that decodes H.264 and a video