Displaying 20 results from an estimated 900 matches similar to: "Tablegen pattern: How to emit a SDNode in an output pattern?"
2018 Jun 21
2
add new instruction format
Hi
Im trying to add RISC V Store Instruction for an Experiment on my Target.
The thing is, llvm Store Format gets Register and Pointer Type Operand.
beside this, RISC-V Store Instruction takes source Register, Base Register and offset immediate type. So this takes 3 leafs.
In this case, should I make new SelectionDAG Node in this case? or use BuildMI Instruction to add new Register?
P.S.
2016 Oct 02
2
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
Previously we'd end up with an unnecessary mov for the thirs immediate value.
total instructions in shared programs : 851881 -> 851864 (-0.00%)
total gprs used in shared programs : 110295 -> 110295 (0.00%)
total local used in shared programs : 1020 -> 1020 (0.00%)
local gpr inst bytes
helped 0 0 17 17
2016 Oct 02
2
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
On 02.10.2016 20:03, Ilia Mirkin wrote:
> On Sun, Oct 2, 2016 at 1:58 PM, Tobias Klausmann
> <tobias.johannes.klausmann at mni.thm.de> wrote:
>> Previously we'd end up with an unnecessary mov for the thirs immediate value.
>>
>> total instructions in shared programs : 851881 -> 851864 (-0.00%)
>> total gprs used in shared programs : 110295 -> 110295
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++-------
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
2009 May 08
0
[LLVMdev] Question on tablegen
Manjunath,
I had a very similar problem and I solved it using a custom vector shuffle and addition instead of mov.
For example,
Vector_shuffle s1, s2, <0,3> is mapped to a custom instruction where I transform the swizzle to a 32bit integer mask and an inverted mask.
So I have dst, src0, src1, imm1, imm2
And I have my asm look similar to:
Add dst, src0.imm1, src1.imm2 and then in the asm
2009 May 19
1
[LLVMdev] TableGen pattern
Hello,
I am trying to convert the subtree (vector_shuffle v2f32, v2f32
(build_vector imm1, imm2)) to a machine instruction that takes 2
v2f32's and 2 immediates. I tried the following table gen pattern :
(set v2f32Reg:$dst, (vector_shuffle v2f32Reg:$src1, v2f32Reg:$src2,
(build_vector
imm:$c1, imm:$c2)))
Table gen barfs about type
2012 Sep 03
1
[LLVMdev] Selection DAG output as bare DAG, code review
Hello all,
I recently foudn myself wanting to view the basic blocks in the
selection DAG as pure DAGs - so just as a list of edges, with no other
information. I added the below code to the start of the "
void SelectionDAGISel::CodeGenAndEmitDAG()" function. It creates a
separate txt file for each basic block and gives a list of edges
between nodes. The segment of code is below -
2019 Nov 22
2
Tablegen PAT limitation?
def STOREbos { // InstructionEncoding Instruction RPPInst RPPInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 1, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2019 Nov 25
2
Tablegen PAT limitation?
You are welcome.
I changed the pattern, the same old error pop up again, crash in the same place.
Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
2015 Sep 18
5
multiply-accumulate instruction
I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target.
The documentation for the processor is as follows:
===
To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made
2019 Nov 21
2
Tablegen PAT limitation?
Hi Krzysztof,
Today I try it on llvm9.0.0 version.
def bos : RPPInstMMEMrr<OPC_STORE,
(outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift),
!strconcat(opcodestr, ""), "$rs1,
2019 Nov 20
4
Tablegen PAT limitation?
Hi,
The full trace stack:
Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
[ 85%] Building X86GenEVEX2VEXTables.inc...
#0 0x000000000081b9b5
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
On Thu, 13 Dec 2018 at 21:41, Friedman, Eli <efriedma at codeaurora.org> wrote:
>
> On 12/13/2018 6:25 AM, Alex Bradbury wrote:
> > There's also likely to be cases where you want to calculate the demanded bits
> > in order to determine if e.g. a W-suffixed instruction can be selected for
> > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match
2014 Mar 06
2
'parallel' package changes '.Random.seed'
Hi,
I've implemented parallelization in one of my packages using the
'parallel' package -- many thanks for providing it!
In my package I'm importing 'parallel' and so added it to the
DESCRIPTION file's 'Import:' tag and also added a
'importFrom("parallel", ...)' statement in the NAMESPACE file.
Parallelization works nicely, but my package
2015 Sep 21
2
multiply-accumulate instruction
I've been looking to see if there's a way to get the instruction below (SMAC) emitted from a higher-level construct, but I'm starting to think this is unrealistic.
To do so, I'd have to tie-in two other instructions: Firstly, clearing the ASR18 and Y register somewhere near the start of the method, then copying out the value of these registers somewhere near the end of the method,
2017 Dec 15
2
InstAlias with tied operands - can it be supported?
Hello,
InstAlias does not allow tied operands (repeated operands) in the asm
string to be matched.
It seems this situation is explicitly prevented in
AsmMatcherEmitter.cpp:
if (!Hack)
PrintFatalError(TheDef->getLoc(),
"ERROR: matchable with tied operand '" + Tok +
"' can never be matched!");
2016 Oct 02
0
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
On Sun, Oct 2, 2016 at 1:58 PM, Tobias Klausmann
<tobias.johannes.klausmann at mni.thm.de> wrote:
> Previously we'd end up with an unnecessary mov for the thirs immediate value.
>
> total instructions in shared programs : 851881 -> 851864 (-0.00%)
> total gprs used in shared programs : 110295 -> 110295 (0.00%)
> total local used in shared programs : 1020 ->
2003 Mar 20
1
bind blocking rsync
Hi Guys,
Here is the setup.
LVS NAT cluster with director (dir), backup director (bdir), and two
realservers (rs1 and rs2) running apache webserver.
SSH DSA key-based authentication set up between rs1 and rs2 in order to
facilitate automated (via cron) mirorring of htdocs directories. All
works fine untill I decide to host DNS on the same cluster. As soon as I
start BIND on rs1, ssh no longer
2018 Dec 13
2
Dealing with information loss for widened integer operations at ISel time
As previously discussed in an RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, the
RISC-V backend has i64 as the only legal integer type for the RV64 target.
Thanks to variable-sized register class support, this means there is no need
for duplication of either patterns or instruction definitions for RV32 and
RV64. It's worth noting that RV64I is a different base
2013 Mar 31
10
Debootstrapping a rootfs for Xen on FastModels A15
Hi,
I''ve tried several different approaches to debootstrap a working
rootfs for with a Cortex A15 model ( FastModels ) and Xen but still
face some issues.
Some information on my setup.
For a Dom0 kernel I''m using the latest version from
git://github.com/torvalds/linux.git, I attached my config as it might
be of some use for others. I''m using the latest Xen unstable