similar to: Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0

Hi Martin, Pseudo CALLSEQ_START was changed in r302527, commit message contains details on the changes. However CALLSEQ_END was not modified. If your made changes to ADJCALLSTACKUP to add additional argument, that may result in error. Thanks, --Serge 2017-09-15 19:09 GMT+07:00 Martin J. O'Riordan via llvm-dev < llvm-dev at lists.llvm.org>: > Hi LLVM-Devs, > > I have managed

Hi Serge, Thanks for your help. I have looked at the change log, and so far as I can tell, my implementation is pretty much identical to all of the in-tree targets, but I’m missing something and can’t see what it is. I have simplified my TD description to just: def MyCallseqStart : SDNode<"ISD::CALLSEQ_START", SDCallSeqStart<[SDTCisVT<0, i32>,

Can you sum a few columns at a time? I tried x =Calc.find(:all, :select => "sum(amt1) amt1, sum(amt2) amt2" :conditions => ["where date > ?", date] ) The sql seems to function properly, but I wasn''t able to grab the values. These just failed x.amt1 x.send("amt1") I tried changing up the query to use sum(amt1) as amt1 sum(amt1)

Hello, I have data frame like the one created below, ##input data Person <- c(1,1,1,1,1,1,2,2) Amount <- c(100,10,100,10,100,10,50,150) Date <- c("12/01/2012", "12/01/2012", "01/01/2013","01/01/2013","02/01/2013","02/01/2013","12/01/2012","12/01/2012") df <- data.frame(Person,Amount,Date) I would

On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote: > Hello, > > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a

Hi, I am creating a new backend for a custom microcontroller. In order to create the backend I am modifying from Mips backend. My architecture has a store instruction with direct address mode. It accepts two arguments: source register and address (immediate). This instruction is not available in Mips, but it is in Hexagon, so I copied from Hexagon the following, adapting it to my registers: -

Hello, I'm working in adding support for 64-bit integers to my target. I'm using LLVM to decompose the 64-bit integer operations by using 32-bit registers wherever possible and emulating support where not. When looking at the bit shift decomposition I saw what seems to be a bug in the implementation. The affected function is ExpandShiftWithUnknownAmountBit in LegalizeIntegerTypes.cpp.

Hi all, hope someone can help me out with this. Background Introduction I have a data set consisting of data collected from a questionnaire that I wish to validate. I have chosen to use confirmatory factor analysis to analyse this data set. Instrument The instrument consists of 11 subscales. There is a total of 68 items in the 11 subscales. Each item is scored on an integer scale between 1 to 4.

I've got a user that wants Japanese language support in firefox... our *stock* CentOS firefox, 24.3. I've yum installed i18, and i10, and no joy. Looked at firefox addons, and there's one, 27.0. Won't install, "not compatible". Neither is either 24.0, or 25.0. Anyone have a link to a compatible version? mark

Hello devlopers, I request your guidance on how to lower the metadata attached with an instruction. Following is given the IR dump before Module verifier pass, and there is a string "Tile3" attached as metadata with instruction "%x = alloca i32, align 4, !Tile3 !1". My target is to transmit/propagate the string down to post RA-Scheduling pass. Is it possible? If yes, how

Hello All, I am trying to understand the demanded-bits pass. The example in the source code (below) seems quite explicit. In the example, only 16 bits from a 32 bit variable in IR are demanded and therefore the variable is truncated to a 16 bit variable. %1 = add i32 %x, %y %2 = trunc i32 %1 to i16 However I was wondering if for example, the addition demanded, say 18 bits, would this pass

Hello: When I use SPSS I execute the AGGREGATE DATA comand for the next data: 2112141123212213212213334 3143244113442312121213344 2114141123112214212113344 2112211122212413421213221 3114444123442414343413344 2312231223212222323223322 2143241123212313131213234 2113241113212313222213333 2113141123112214212113344 2114141123412111114413344 2113211122342314222313234 2114141123112414212113344

I'm working through some very basic IR code and got a bit confused by the string printing example. In particular, if you have a constant string like: @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00" To pass this as a pointer to a C-function like printf you need to use 2 indexes in getelementptr: %sp = getelementptr [4 x i8]* @.str, i32 0, i32 0 I think I understand

On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote: > > def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; > > > I think for setting an implicit register, you still need to have 1 result > here. > > If you look at

My understand is that in DAG terminology, Flag is now called Glue. It would be nice for someone to go through and clean up the code as far as comments and variable names. That was driving me close to the brink of insanity till I found out about this. Even in Selection Dag Node Properties def SDNPOutGlue : SDNodeProperty; // Write a flag result def SDNPInGlue : SDNodeProperty;

> > > > > def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, > SDTCisVec<1>, > SDTCisSameAs<2, 1>]>; > > This is confusing to me. This tells me that there is 1 result but and 2 > operands. But then it says that operands 2 and 1 are of the same type,

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

On Tue, Feb 2, 2016 at 1:41 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Let me clarify. >> >> I'm not sure I understand what you are saying. Let me post more >> information. >> >> Here is what I have defined for Escalasetflag >> >> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag, >>

Hello everybody, I have stumbled upon a test case (the attached module is a slightly reduced version) that shows extremely reduced performance on linux compared to windows when executed using LLVM's JIT. We narrowed the problem down to the actual code being generated, the source IR on both systems is the same. Try compiling the attached module: llc -O3 -filetype=asm -o BAD.s BAD.ll Under

Hello all - I am sorry if this simple question is addressed in somewhere else. But, I couldn't find it. It's been for about a week using R. . . My problem is: Reading matrix data with "scan" does not seem to allow me to incorporate matrix labels (columns, and rows). If I use read.table, I can import the lables. But, the problem is, I don't know how I make this data as