similar to: Question about quad-register

Hi Anton, I assume that's the same as the online demo's "Show LLVM C++ API code" option (http://llvm.org/demo/)? I've tried that with a structure containing four floating-point components but it also appears to add them individually using extract/insert. Maybe I have to try an array of floats... Thanks, Anton -----Original Message----- From: llvmdev-bounces at

Nicolas, > Thanks for the advise, but I'm actually not trying to compile code from > text. For now I'm just trying to construct the function directly. Think of > it as the vector equivalent of the HowToUseJIT.cpp example. llvm2cpp is your friend then. It's now a separate 'target' in llc. It will generate C++ code, which will construct provided IR. -- With best

GCCBuiltin just gives it a name for clang to lookup. Generally they match up with builtins that gcc also implements, but that's not a requirement. If you add a builtin with the same name to the builtin file in clang's include/clang/Basic/Builtins*.def then they will find each other. You can also just add a builtin to clang's builtin file and catch it in clang's

I've created an intrinsic from my target, but I can't figure out how I can run it from a C code. Most of the targets have a GCCBuiltin and it looks like it is the way to execute an intrinsic from C code. However in my case there is no actual GCC built in. Any help on this is really appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part

Does anyone know exactly what ComposerIndices in Target.td is all about? I see just one place where it's used in X86 but it's not clear from the comments in Target.td and it's one usage, exactly what this feature is about. Tia. Reed

On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote: > > On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: > >> On Mon, 23 Apr 2007, Christopher Lamb wrote: >>> How can one let the back end know how to insert and extract >>> elements of >>> a vector through sub-register copies? I'm at a loss how to do >>> this... >> >> You

Hi Richard, Thanks for working on this. We should probably move this discussion to llvm-dev because it is not strictly related to the patch review anymore. The code below is not representative of general c/c++ code. Usually only domain specific language (such as OpenCL) contain vector instructions. The LLVM pass manager configuration (pass manager builder) is designed for C/C++ compilers, not

Hi folks, TableGen provides sufficiently rich syntax for expressing target instruction set. Nevertheless, when I wrote the PTX backend, I observed that some redundancy in TableGen can be further eliminated through macro expansion of for-loops. The semantics of a for-loop is expanding the for-loop body, and so it is equivalent to manually unroll the loop (see example #1). I believe the for-loop

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > should look into, > > // Integer registers > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > ... That's the easy part. ARM (AArch32) has 16 registers

Hi, I want to increase the number of integer registers in the ARM machine. I don't have any idea how/where I can start. Can anybody help me? By the way, what are the following line in the ARMRegisterInfo.td specify: def qsub_0 def qsub_1 .... Thanks Best Regards, A. Yazdanbakhsh

I have a register hierarchy that looks like a binary tree. v4 -> {v2, v2} -> {s, s}{s, s}(or, {x, y}, {z, w}) I have an instruction that can access the 2nd and/or 4th scalar and an instruction that can access the 1st and/or 3rd scalar. What I need to do is that given the first scalar, I need to be able to select the 2nd scalar, or/and given the 3rd, select the 4th. I define a sibling

On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote: > On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote: > >> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: >> >>> On Mon, 23 Apr 2007, Christopher Lamb wrote: >>>> How can one let the back end know how to insert and extract >>>> elements of >>>> a vector through sub-register

Hi Micah, This sounds somewhat similar to what ARM uses for the stride-by-two vector load instructions. For example, Tuples2DSpc. While not exactly what you're looking for, perhaps something along those lines would work? -Jim On Jul 17, 2012, at 3:24 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I have a register hierarchy that looks like a binary tree. >

On Wed, Dec 05, 2012 at 09:17:12PM -0600, Amir Yazdanbakhsh wrote: > Hi, > > I want to increase the number of integer registers in the ARM machine. > I don't have any idea how/where I can start. Can anybody help me? The code below in lib/Target/ARM/ARMRegisterInfo.td is where you should look into, // Integer registers def R0 : ARMReg< 0, "r0">,

The field Num seems to have no meaning. It is not recognized by the backend tools. It does not hurt anything but should not be there. // We have banks of 32 registers each. class MipsReg<string n> : Register<n> { field bits<5> Num; let Namespace = "Mips"; } class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {

On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote: > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > > > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > > should look into, > > > > // Integer registers > > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > > def R1 : ARMReg< 1,

Ok, I've been looking at this for hours and can't figure it out. I know I'm missing something obvious. I've been spending the past few days beefing up the vector support in the C Backend. This should help us debug vector code that's miscompiled. But gcc doesn't like this fragment: ((double *)(&llvm_cbe_r1147))[0u] = (((llvm_cbe_r1146__BITCAST_TEMPORARY.Int64 =

Hi Devs, Consider below testcase. $cat test.cpp #include <vector> #include<type_traits> typedef int _int4 __attribute__((vector_size(16))); typedef union{ int data[4]; struct {int x, y, z, w;}; _int4 vec; } int4; typedef int4 int3; int main() { static_assert(std::alignment_of<int4>::value <= alignof(max_align_t), "over aligned!"); } $clang++ -m32 error:

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> Hi Rail, >> >> Two hints to begin with: >> >> 1) Makes sure you example is