Displaying 20 results from an estimated 400 matches similar to: "When to use auto instead of iterator/const_iterator?"
2014 Dec 14
2
[LLVMdev] ScheduleDAGInstrs.cpp
Hello again,
Sorry -- I think I found the problem somewhere else. I was a bit confused and missed the fact that adjustChainDeps() is called a few lines down and does just what I wanted :-)
I would like to instead ask another question:
Why is I->isCtrl() used in code like
// Iterate over chain dependencies only.
for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E =
2014 Dec 16
3
[LLVMdev] ScheduleDAGInstrs.cpp
Hi,
Thank you for the reply.
>It looks to me like we can choose any subset of edges here and be correct. We're basically trying to prune/pinch the DAG edges here. They can easily blow up with AA sched. I would guess that isCtrl() edges are good ones to bypass because they could be a low-latecy edges, whereas true data dependencies from a load are expected to be >higher latency, so they
2014 Dec 08
3
[LLVMdev] ScheduleDAGInstrs.cpp
Hi,
Can anyone help me to understand the ScheduleDAGInstrs::buildSchedGraph() method?
I find the handling of AliasChain is disturbing since:
1. A new alias chain add deps to all possibly aliasing SUs, and then clears those lists.
2. When AliasChain is present, the addChainDependency() method is called,
but the target hook areMemAccessesTriviallyDisjoint() called inside
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
Andy,
Thanks for reply. I was able to trace the problem to the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
Andy,
I traced my problem to this point:
In ScheduleDAGInstrs.cpp we have the following function:
/// addVRegDefDeps - Add register output and data dependencies from this
SUnit
/// to instructions that occur later in the same scheduling region if they
read
/// from or write to the virtual register defined at OperIdx.
///
/// TODO: Hoist loop induction variable increments. This has to be
///
2013 Aug 22
2
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
Hi
I have brought everything together in this email.
The problem
========
Take the following DAG (arrow to predecessor):
SetUp2 SetUp1
^ ^
| |
| |
Destroy2---->PredSU <----SU
^ ^ ^
| | |
| | |
----------- | ---------
2013 Aug 22
0
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
On Thu, Aug 22, 2013 at 4:15 AM, Robert Lytton <robert at xmos.com> wrote:
>
>
> Outstanding issues
> ============
>
> 1. Is it too aggressive in searching predecessors and successors?
> Should the algorithm give up and assume the worst if the depth of
> search reaches a predefined limit?
>
> 2. Should the initial search for 'SetUp1' and
2014 Jan 17
3
[LLVMdev] Artificial deps and stores
Andy, et al.,
In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this:
if (!ExitSU.isPred(SU))
// Push store's up a bit to avoid them getting in between cmp
// and branches.
ExitSU.addPred(SDep(SU, SDep::Artificial));
This code does not seem to be in any way specific to compares; and in any case, at least on the PPC A2, scheduling stores in
2014 Jan 18
3
[LLVMdev] Artificial deps and stores
On Jan 17, 2014, at 4:03 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Jan 17, 2014, at 3:54 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
>> Andy, et al.,
>>
>> In ScheduleDAGInstrs::buildSchedGraph, the code for handling stores has this:
>>
>> if (!ExitSU.isPred(SU))
>> // Push store's up a bit to avoid them
2011 Jun 18
0
[LLVMdev] Custom Static Scheduling
Hi,
On 06/18/2011 06:26 AM, Benjamin Müller wrote:
> i created a Function Pass to retrieve the Control/Data Flow Graph from
> a simple program,
> now i would like to statically schedule the Instructions. Is this
> possible by starting to modify the SelectionDAG Files ?
> Or can i even build a "standalone" custom scheduler?
> Thank you very much for any tipps.
You
2011 Jun 18
2
[LLVMdev] Custom Static Scheduling
Hi there,
i created a Function Pass to retrieve the Control/Data Flow Graph from
a simple program,
now i would like to statically schedule the Instructions. Is this
possible by starting to modify the SelectionDAG Files ?
Or can i even build a "standalone" custom scheduler?
Thank you very much for any tipps.
Ben
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> So if this early exit is taken:
>
> // SSA defs do not have output/anti dependencies.
> // The current operand is a def, so we have at least one.
> if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
> return;
>
> we do not ever get to this point:
>
>
2011 Nov 24
1
[LLVMdev] Scheduler information
[LLVMdev] tag added, sorry for duplicated message.
Hi list,
Could someone help me to understand the internal data dependecy
structure used by the scheduler ?
As far as I can see in /lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp,
SUnit nodes are created to wrap SDNodes with scheduling related
information and SDeps represent all kind of dependencies between them.
Nevertheless, I cannot figure
2006 Jul 04
2
[LLVMdev] Critical edges
On Tue, 4 Jul 2006, Fernando Magno Quintao Pereira wrote:
> However, it does not remove all the critical edges. I am getting a very
> weird dataflow graph (even without the Break Critical edges pass). The
> dataflow generated by MachineFunction::dump() for the program below is
> given here:
> http://compilers.cs.ucla.edu/fernando/projects/soc/images/loop_no_crit2.pdf
...
> The
2012 Nov 01
2
[LLVMdev] Undef registers in dependency graph
Hi,
I see that currently physical register uses marked as "undef" can still
cause dependencies. Is this intentional?
SU(9): %D5<def,undef> = LDrid %R0, 0, %R10<imp-def>, %R11<imp-def>
# preds left : 0
# succs left : 11
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Successors:
...
2013 Aug 22
0
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
sorry,
Just noticed that the diagrams have 'Destroy' & 'SetUp' the wrong way around!
Robert
________________________________
From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of Robert Lytton [robert at xmos.com]
Sent: 21 August 2013 18:34
To: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in
2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Quentin,
I have rerun the test case on a recent commit, so the numbers have changed. There are also now a few more basic blocks very small basic blocks in the function, and therefore there are some slight differences. I tried to go back to earlier commits, without success for some reason... This is however very similar, except that there becomes two COPYs back to sibling value after the loop.
2016 Sep 21
2
Propagation of debug information for variable into basic blocks.
> On Sep 21, 2016, at 2:23 PM, Daniel Berlin <dberlin at dberlin.org> wrote:
>
>
>
> // For all predecessors of this MBB, find the set of VarLocs that
> // can be joined.
> for (auto p : MBB.predecessors()) {
> auto OL = OutLocs.find(p);
> // Join is null in case of empty OutLocs from any of the pred.
> if (OL == OutLocs.end())
>
2014 Dec 09
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Jonas,
Thanks for your patience.
After spending some time looking at the additional output you gave me, I agree that your fix is the right one.
I was worried that this problem may arise because we were spilling not real user, but in fact what I thought was the problem is an optimization we could do :).
See my comments inlined for a few nitpicks before you commit.
Thanks again,
-Quentin
On
2013 Aug 21
2
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
Hi,
I have reasoned through and believe the problem is with the PrescheduleNodesWithMultipleUses.
Take the following DAG (arrow to predecessor):
Destroy Destroy
^ ^
| |
| |
SetUp----->PredSU <-----SU
^ ^ ^
| | |
| | |
----------- |