similar to: isSSA computation in MIR parser

Hi, I found that prologue_end markers where badly placed in my test, and applied https://reviews.llvm.org/D41762 in the hope that it would fix it (I'm on 4.0.1). However, this fix doesn't work for VLIW architectures. At this point we're iterating over bundles, not MachineInstructions, and the FrameSetup flag is set on MachineInstructions, not bundles. If bundling happens in the

Hi, anyone know anything about copy propagation? Matthias, I see this was your code originally? Was there some assumptions you made? I'm hitting an assertion in MachineCopyPropagation::isNopCopy: if (Src == PreviousSrc) { assert(Def == PreviousDef); return true; } This code compares two COPY instruction to see whether they are effectively "the same". The assert assumes

Can I assume we're talking about MCJIT since a file format and relocations are involved? Some changes are required in order to get MCJIT to generate ELF object files. Eli Bendersky submitted a patch some time ago to modify the target triple code to enable this, but after a bit of discussion there didn't seem to be a consensus for accepting this proposal. If you want to try it out, the

Hi, In X86MachObjectWriter::RecordX86Relocation I found the comment if (Target.isAbsolute()) { // constant // SymbolNum of 0 indicates the absolute section. // // FIXME: Currently, these are never generated (see code below). I cannot // find a case where they are actually emitted. Type = macho::RIT_Vanilla; } Is the FIXME still true? I've got some code that

Hi Jim, Andrew, Thanks, I read the discussions about using ELF + MCJIT + Windows and was hoping MachO would work just as well. Since you don't need to modify LLVM to be able to output MachO this was my first choice. But are you saying MachO will not work as well as ELF? Thanks for the patch Andrew, that will have to be my plan B in this case. Verena On 29/06/2012 23:47, Kaylor, Andrew

Hi Verena, Windows + MachO is likely to run into lots of problems once you start passing in non-trivial code. The relocation model is very tied to Darwin. I believe some folks doing JIT on Windows have had some success w/ ELF. Hopefully someone more familiar with the specifics of that will chime in. -Jim On Jun 29, 2012, at 8:58 AM, Verena Beckham <verena at codeplay.com> wrote: >

Hi there, I wondered whether anyone could give me any advice about counting assembly instructions when using MCJIT? For performance regression testing I would like to be able to count the number of instructions generated during the jit compilation of a given module. The Statistic class, as far as I understand, cannot collect this data per-module (per-ExecutionEngine/per-MCJIT), and there is

Hi All, I have a question about TableGen RegisterClass definition. I need to map different size of MVTs into a register class as below. def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...> When I look at TableGen and CodeGen, it looks the types are used as following: 1. MCRegisterClass's RegSize and Alignment 2. SpillSize in TableGen 3. Type constraint for instruction

Hi, I think there might be a bug in the tail duplicator (called from MachineBlockPlacement in my case), when duplicating a block that contains an implicit fall-through. Suppose you have the following blocks BB#1: Predecessors according to CFG: BB#2 ... conditional_branch <BB#3> < implicit fall-through to BB#2 > Successors according to CFG: BB#2 BB#3 BB#2:

Hi Verena, I think that we can count the number of instructions with "-stats" command line option. As you mentioned, this option uses Statistic class like "STATISTIC(EmittedInsts, "Number of machine instrs printed");" I don't know exactly about parallel code generation environment but this option seems like to work correctly in common case as following. This is

Just be aware that those ifdefs were recommitted and reverted several times, so I'm not sure what the state is. On Fri, Sep 28, 2018 at 8:48 AM Alastair Murray via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi Kern, > > We also had issues with mixing GCC/Clang builds when testing the 7.0 > release branch. > > My colleague submitted a patch that fixed the issue

Hi folks, Not sure if this is the right mailing list target, but I'm trying out the new LLVM 7.0 packages found at http://apt.llvm.org by porting over an existing LLVM 6.0 project of ours to the new version. In doing so, I found that the executable always segfaulted at the same spot with no explanation: 0x0000000000fefe33 in

Thu Jul 12 03:42:12 CDT 2012, Verena Beckham verena at codeplay.com : > I would not say it is trivial, having done it myself. > > MCJIT also doesn't support multiple modules, and it does not do JITing > on demand, instead, it does all of it at the same time in the > constructor (unless that is what you call "not lazy"). > So depending on how you've written your

Hi Pawel, Some of the issues I have come across (from memory!) are * MCJIT doesn't work on Windows, because it doesn't support COFF. If you want to use it on Windows you have to either target Mach-O (not clear whether that will work in general) or ELF (need to get a patch from Intel to be able to use this). * Make sure you include MCJIT.h and link in MCJIT.lib, otherwise (even if

Hello everyone, Consider we have this following set of code: int foo() { int a,b; a = __builtin_XX(0x11); b = __builtin_XX(0x11); return a+b; } The problem currently is that LLVM eliminated the second call and copied the result from the first call into a new set of registers. Is there is a way to force LLVM to generate two explicit calls to a builtin function. The builtin takes in an integer

Hi list, I happened to read below thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def

Thanks Andrew. I have tried with recent tblgen, ReadAdvance would not work for multiple latencies. Maybe I should make improvement into tblgen if Pierre-Andre does not have the change anymore. However, I just a little curious about the situation I met. The hardware forwording may fail for different reasons, which different register read may have different latencies, depending both on the register

On 06/11/2018 02:33 PM, Friedman, Eli via llvm-dev wrote: > On 6/11/2018 10:06 AM, jingu at codeplay.com via llvm-dev wrote: >> Hello All, >> >> I have met one may-alias case from llvm's alias analysis. The code >> snippet is as following: >> >> char buf[4]; >> >> void test (int idx) { >> char *a = &buf[3 - idx]; >> char *b =

Hi, You cannot call removeModule on a JIT with no modules: jitstate will be 0 and therefore we have a null-pointer exception. The function returns a boolean for success/failure, however, so you would expect to be able to call it and get false back. Should we be checking for jitstate != 0 before accessing the variable? - if (jitstate->getModule() == M) { + if (jitstate &&

On Tue Jan 14, 2020 at 8:27 PM, Reid Kleckner wrote: > I don't think there's any technical reason for the current structure. Apparently [this](https://docs.microsoft.com/en-us/cpp/cpp/compiler-limits?view=vs-2019) is a thing. This results in the following delight happening on Visual Studio 2015: > fatal error C1091: compiler limit: string exceeds 65535 bytes in length So maybe