Displaying 17 results from an estimated 17 matches similar to: "error: In anonymous_4820: Unrecognized node 'VRR128'!"
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
Thank You.
How to do the same for add please see the following; it gives duplication
error.
def VADD : I<0x0E, MRMDestReg, (outs VRR128:$dst), (ins VRR128:$src1,
VRR128:$src2),"VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set
VRR128:$dst, (add VRR128:$src1, VRR128:$src2))]>, TA;
def : Pat<(add VRR128:$src1, VRR128:$src2), (VADD VRPIM128:$src1,
VRPIM128:$src2)>;
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
Thank You.
But can we use same register class for fadd as well,
is this instruction correct?
def VFADD : I<0x0E, MRMDestReg, (outs VRR128:$dst), (ins VRR128:$src1,
VRR128:$src2),"VFADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set
VRR128:$dst, (fadd VRR128:$src1, VRR128:$src2))]>, TA;
On Tue, Jul 11, 2017 at 9:00 PM, Craig Topper <craig.topper at gmail.com>
wrote:
>
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Hello,
i want to work with these types v32f32, v32f64.... in llvm which are
undefined in the backend?
But v32i32, v32i64 are already defined so i am able to use these.
but for other types such as v32f32, v32f64 although i have defined them
appropriately in all the files like machinevaluetype.h, valuetypes.cpp
etc. i have checked it many times but still getting the following error
when build in
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Thank you so much. it run fine.
Can you please resolve following issue;
I now have support for v2048i32
but my backend supports v64i32
so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the
only difference between 2 is if its orginally v2048i32 i want my registers
assignment from REG_A set. if its v64i32 originally, then i want registers
from set REG_B.
How to accomplish
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
I would be very grateful if you specify whether there is some way to
allocate registers (different order) / from different register sets to the
same instruction based on the vector width/ no of iterations.
I have tried several alternatives but could not succeed.
Also I have asked this question many times but no one responds.
Is there something wrong with this??
Kindly guide me.
Thank You
On
2020 Jun 30
5
[RFC] Semi-Automatic clang-format of files with low frequency
I 100% get that we might not like the decisions clang-format is making, but
how does one overcome this when adding new code? The pre-merge checks
enforce clang-formatting before commit and that's a common review comment
anyway for those who didn't join the pre-merge checking group. I'm just
wondering are we not all following the same guidelines?
Concerns of clang-format not being good
2017 Sep 21
1
VSelect Instruction Error
Hello,
I am getting this error. What instruction is required to be implemented?
LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16
t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>,
undef:i64
t659: i64 = FrameIndex<1>
t10: i64 = undef
t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0,
t8, undef:i64
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
hello,
i have a situation where i have to assign the registers to instructions
based on the loop iterations.
for eg..
the registers are:
R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3,
R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3,
R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3.
These registers defined in object Reg_A
These are total 12 registers. will use them contiguously, here i define it
in above mentioned order i.e
2018 Jul 24
2
KNL Vectorization with larger vector width
Thank You.
Right now to see the effect i did following changes;
unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasAVX512())
return 65536;
here i changed 512 to 65536. Then in loopvectorize.cpp i did following;
assert(MaxVectorSize <= 2048 && "Did not expect to pack so many elements"
" into
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
Here basically my problem is vector width since i have used v64i32 in my
backend. now if vector width=64. i want the Reg_B class registers to be
assigned and if vector width=2048 i want Reg_A registers to be assigned to
instruction.
Should i incorporate the solution in lowering stage? some thing like;
addRegisterClass(MVT::v2048i32, &X86::Reg_B);
2018 Jul 24
2
KNL Vectorization with larger vector width
Hello,
I need help here. I am able to adjust the vector width through
WidestRegister value. When number of iterations=31 and I set vector
width=32 it gives <16xi32> and <8xi32> instructions.
However if i replicate same behavior with number of iterations=63 and I
set vector width=64, no vector instructions are emitted. it should do as
previous and gives <32xi32> and
2019 Jul 18
2
Question about TableGen RegisterClass definition
Hi All,
I have a question about TableGen RegisterClass definition.
I need to map different size of MVTs into a register class as below.
def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>
When I look at TableGen and CodeGen, it looks the types are used as following:
1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction
2017 Aug 07
3
VBROADCAST Implementation Issues
Thank You. Still getting errors.I have modified my instructions as you said
as follows:
def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, VK64WM:$mask_wb),
(ins VR_2048:$src1, VK64WM:$mask, i2048mem:$src2),
"GATHER_256B\t{$src2, {$dst} {${mask}}|${dst}
{${mask}}, $src2}",
[(set VR_2048:$dst, VK64WM:$mask_wb, (v64i32
(masked_gather
2017 Aug 07
2
VBROADCAST Implementation Issues
Hello,
I did as you said,
Please tell me whether the following correct now??
def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, _.KRCWM:$mask_wb),
(VR_2048:$src1, _.KRCWM:$mask, ins i2048mem:$src2),
"GATHER_256B\t{$src2, {$dst}{${mask}}|${dst} {${mask}},
$src2}"),
[(set VR_2048:$dst, _.KRCWM:$mask_wb, (v64i32
(GatherNode
2017 Aug 06
2
VBROADCAST Implementation Issues
i want to implement gather for v64i32. i wrote following code.
def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins
i2048mem:$src),
"GATHER_256B\t{$src, $dst|$dst, $src}",
[(set VR_2048:$dst, (v64i32 (masked_gather
addr:$src)))],
IIC_MOV_MEM>, TA;
def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B
2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You. I got it. Version issue.
TTI.getRegisterBitWidth(true)
How to put my target machine info in TTI?
Please help.
On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote:
>
> Thank You.
>
> But I cannot find your mentioned function
2015 Sep 11
0
[ANNOUNCE] intel-gpu-tools 1.12
A new intel-gpu-tools quarterly release is available with the following changes:
- Various new tests and tools
- New statistical analysis functions. (Damien Lespiau)
- New benchmark tests. (Chris Wilson)
- Old register tools that were superseded by intel_reg have been removed.
- Various tests have been marked "basic", to indicate they are suitable for
use in basic acceptance