Displaying 20 results from an estimated 5000 matches similar to: "Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'"
2017 Aug 22
3
Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
On 08/22/2017 03:59 AM, Alex Bradbury via llvm-dev wrote:
> On 21 August 2017 at 13:23, Martin J. O'Riordan via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
>> But there is a downside.
>>
>> For each of the above I also have variations that are a result of different
>> processor and ISA versions, and because of this I have to use
>> ‘multiclass/defm’
2017 Aug 23
3
Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
On 08/23/2017 12:44 PM, David Chisnall wrote:
> On 23 Aug 2017, at 18:21, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> On 08/23/2017 12:06 PM, Krzysztof Parzyszek via llvm-dev wrote:
>>> On 8/23/2017 11:58 AM, Hal Finkel via llvm-dev wrote:
>>>> If we want to go down that route, I can certainly imagine a feasible
2012 Aug 06
2
[LLVMdev] Tablegen foreach
That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
multiclass instmcRegImm<...> {
def rr: inst<...>;
def ri: inst<...>;
def ir: inst<...>;
def ii: inst<...>;
}
multiclass instmc<...> {
defm i8 : instmcRegImm<...>;
^-- repeat for 15
2012 Aug 06
0
[LLVMdev] Tablegen foreach
I believe multiclasses can be nested. Could that help you reduce the
duplication?
--Sean Silva
On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
>
> multiclass
2007 Sep 13
1
[LLVMdev] Nested multiclass/defm declarations?
Hi list,
I'm toying with the idea of writing a m680x0 backend for LLVM, and the
address modes of this chip are bewildering, to say the least. Here's a
rough list off wikipedia for reference:
* Register direct
o data register, e.g. "D0"
o address register, e.g. "A6"
* Register indirect
o Simple address, e.g. (A0)
o
2017 Aug 23
3
Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
On 08/23/2017 11:35 AM, Jakob Stoklund Olesen wrote:
>
>> On Aug 22, 2017, at 14:15, Hal Finkel via llvm-dev
>> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
>> For situations well beyond TableGen's current language capabilities,
>> we have a decision to make. We can continue extending TableGen until
>> it can
2012 Aug 06
0
[LLVMdev] Tablegen foreach
I think a multiclass may be a better fit for what you are trying to
do. In fact, this is the canonical example for multiclasses:
<http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>.
--Sean Silva
On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> I’m trying to find examples of the foreach pattern being used in
2017 Aug 23
5
Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
On 08/23/2017 12:06 PM, Krzysztof Parzyszek via llvm-dev wrote:
> On 8/23/2017 11:58 AM, Hal Finkel via llvm-dev wrote:
>> If we want to go down that route, I can certainly imagine a feasible
>> incremental-transitioning strategy. We could allow TableGen to use an
>> embedded Python interpreter to generate records based on Python data
>> structures, and then, combine
2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Tue, Feb 10, 2009 at 8:27 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Bill,
> Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
> define other classes, but with using patterns inside of a multiclass to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
> def _i8 : Pat<(sub
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Bill,
Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub
2012 Aug 06
2
[LLVMdev] Tablegen foreach
I'm trying to find examples of the foreach pattern being used in tablegen files.
The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal.
So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations.
Instead of writing all the combinations out, I'd like to use
2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td, et al.
-bw
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On Thu, Jan 14, 2016 at 6:05 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 1/13/2016 4:47 PM, Phil Tomson wrote:
>
>>
>> First off, I got this idea from the LLVM Cookbook chapter 8: Writing an
>> LLVM Backend: Lowering to multiple instructions. (now I'm having my
>> doubts as to whether this is the right approach)
>>
>
>
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Sun, 1 Oct 2006, Roman Levenstein wrote:
> I'm trying to implement a new backend for an embedded CISC processor.
> Therefore I thought that it makes sense to take X86 target as a basis,
> to save some time.
Ok. Note that the X86 backend is one of the most complex though, because
it supports several subtargets and ABIs, which makes it more complex than
some other targets.
>
2012 Nov 14
0
[LLVMdev] TableGen: Requires in multiclass's def as well as defm
Hi,
I'd like to disallow ARM's register-register preload instruction for NaCl
(and keep the register-immediate), and instead of my localmod being to
delete the 'rs' def from multiclass APreLoad I'd like to do the cleaner
thing and have rs require IsNotNaCl. This unfortunately doesn't seem to
work because the subsequent defm have their own Requires.
The way preloads are
2011 May 08
2
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
Hi, all
I am trying to add "not" instruction support to PTX backend.
I add the line below in PTXInstrInfo.td,
defm NOT : PTX_LOGIC<"not", not>;
But I get errors below,
-------------------------------------------------------------------------------
Included from PTX.td:75:
PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type 'SDNode' is
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
Hi Chris,
Thanks a lot for your answer!
Chris Lattner wrote:
>> 1. Why does X86 instruction set description provide different
>> descriptions for the same instructions, which differ only in the
size
>> of operands?
>> E.g.
>>
>> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
>> "mov{b} {$src, $dst|$dst, $src}",
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace =
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate?
-Owen
On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> I am trying to make
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
I'm not at the machine that has the changes, but it was failing at index 0.
Micah
From: Owen Anderson [mailto:resistor at mac.com]
Sent: Thursday, April 19, 2012 3:35 PM
To: Villmow, Micah
Cc: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output