similar to: [PATCH] x86/vtsc: update vcpu_time after hvm_set_guest_time

Hi Ian/Stefano: I changed over to the PV clock for hybrid liked we talked at the hackathon. I still have the hang in update_wall_time() after dom0 switches to xen as clocksource. The source of hang seems to be in xen stime_local_stamp in cpu_time that suddenly jumps to a large 64bit value. I''ve been chasing to figure where that happens, and why for the hybrid and not PV. It appears the

The value of ACPI PM-Timer may be broken on save unless the timer mode is delay_for_missed_ticks. With other timer modes, vcpu->arch.hvm_vcpu.guest_time is always zero and the adjustment from its value is wrong. This patch fixes the saved value of ACPI PM-Timer: - don''t adjust the PM-Timer if vcpu->arch.hvm_vcpu.guest_time is zero. - consolidate calculations of PM-Timer to one

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

Running a heavily modified xen-unstable changset 19590:f80cf52a4fb6 with debugger_attached set, I was seeing the debug traps getting lost from the EXCEPTION_BITMAP in vmx_update_guest_cr() when transitioning from real to protected mode. In my codebase, I could fix this trivially by clearing the debug_state_latch and letting vmx_do_resume() reapply the setting. However, while it looks like a valid

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 _______________________________________________ Xen-devel mailing list

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

I''m not seeing the problem that Fan Zhao is reporting, instead I get this one. Not sure if ti''s the same one or a different problem... This happens with my simple-guest [i.e. not using hvmloader, as I described before]. This worked fine yesterday. (XEN) event_channel.c:178:d0 EVTCHNOP failure: domain 0, error -22, line 178 (XEN) bad shared page: 0 (XEN) domain_crash_sync called

Keir: Not sure from when, at least now hvm_do_resume is double invoked in both 1: arch_vmx_do_resume from schedule_tail, and 2) vmx_asm_do_vmentry of ASM code for both x86 32 & 64 bits. I am wondering if the #1 is a redundant, can u have a double check? thx,eddie _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Hi, Dan, This patch fixes strange behavior on IA64, that IDLE is scheduled more than Dom0 with default sEDF scheduler. The key point is reprogram_ac_timer at the end of ac_timer dispatcher, which programs local apic timer with expire of next ac_timer on x86. Higher precision lapic timer can trigger ac_timer more precisely than simply done in PIT interrupt handler. That works perfectly on x86

If a guest sets a state and dirties the state, but later temporarily clears the state, and at this time if this vcpu is scheduled out, then other vcpus may corrupt the state before the vcpu is scheduled in again, thus the state cannot be restored correctly. To solve this issue, this patch save/restore all states unconditionally on vcpu context switch. Signed-off-by: Weidong Han

flight 18092 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/18092/ Failures :-/ but no regressions. Tests which are failing intermittently (not blocking): test-amd64-amd64-xl-qemuu-winxpsp3 8 guest-saverestore fail pass in 18090 Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-pcipt-intel 9 guest-start fail never pass

From: Yang Zhang <yang.z.zhang@Intel.com> With virtual unrestricted guest feature, L2 guest is allowed to run with PG cleared. Also, allow PAE not set during virtual vmexit emulation. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/hvm.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git

The aim of this patch is to define a stable way in which PVH is going to do AP bringup. Since we are running inside of a HVM container, PVH should only need to set flags, cr3 and user_regs in order to bring up a vCPU, the rest can be set once the vCPU is started using the bare metal methods. Additionally, the guest can also set cr0 and cr4, and those values will be appended to the default values

Hi, I''m a PhD student trying to add some load balancing code to the credit scheduler in order to fit some specific necessities. I''m trying to understand the credit scheduler code and I don''t quite get in which part of it a pcpu starts running a vcpu. I need to keep track of when a vpcu starts running in a cpu and when it stops. Any hint on that? I think that it would

Hi all, Does anyone have thoughts on extending v->arch.hvm_vcpu.single_step to support pre-MTF systems, in a way that would mimic the MTF? So far I''m emulating PUSHF/POPF to hide the hypervisor''s trap flag, and eventually I''ll multiplex it down to the guest, but I''m having issues. Right now, I''m enabling X86_EFLAGS_TF in vmx_intr_assist, just like

Changeset 17716 provides monotonically increasing guest time for HVM domains, by using the per-domain pl_time structure. hvm_get_guest_time and hvm_set_guest_time were changed to use this. Previously, the guest time was stored directly in the TSC offset fields of the vmx/smv control structures. Since pt_freeze_time and pt_thaw_time use hvm_get/set_guest_time, they now no longer freeze TSC

patch revision history ---------------------- v1: Initial patch to handle this issue involving changing the hypercall interface v2:Totally handled inside hypervisor. v3:Change some logics of handling msi-x pending unmask operations. v4:Some changes related to coding style according to Andrew Cooper''s comments v5:Some changes according to Jan''s comments, including a) remove

Hi all, I am having confusion regarding the way a newly created domain is allocated vcpu. Initially during dom0 creation alloc_vcpu is called to create vcpu structs for all the available cpu''s and assigned to dom0. But its not the case for domU creation. 1. So how will dom0 relinquish/share vcpu to/with a newly created domU. Does this happen as part of the shared_info page mapping??