similar to: LWP Interrupt Handler

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

The attached patch fixes the save/restore issue seen with 32bit Windows guest VMs. The root cause is that current Xen doesn''t intercept SYSENTER-related MSRs for 32bit guest VMs. As a result, the guest_sysenter_xxx fields contain incorrect values and shouldn''t be used for save/restore. This patch checks the LMA bit of EFER register in the save/restore code path. Please apply it

This patch enables LWP related CPUID to HVM guests. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi Ian, There have been a lot of interest on gfx passthru recently. This patch enables ATI VBIOS in passthru mode. The guest VM system BIOS (including Windows boot logo) can now show in passthru screen. We have tested with various Windows and Linux guest VMs. Please help review it. We are also looking forward to comments and suggestions from Xen community users. Signed-off-by: Wei Huang

Also, rename to MOVE_CLEANUP_VECTOR to be in line with the other IPI names. This requires bumping LAST_HIPRIORITY_VECTOR, but does mean that the range FIRST-LAST_HIPRIORITY_VECTORs are free once again. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> diff -r 0268e7380953 -r c7884dbb6f7d xen/arch/x86/apic.c --- a/xen/arch/x86/apic.c Mon Sep 05 15:10:28 2011 +0100 +++

This patch changes hap parameter from boolean to integer. So users can disable and enable hap using "hap=0" and "hap=1". It also prints out nested paging message under SVM. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

Future AMD SVM supports a new feature called flush by ASID. The idea is to allow CPU to flush TLBs associated with the ASID assigned to guest VM. So hypervisor doesn''t have to reassign a new ASID in order to flush guest''s VCPU. Please review it. Thanks, Wei Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro

Under the assumption that in these cases recurring faults aren''t a security issue and it can be expected that the drivers there are going to try to take care of the problem. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -625,6 +625,18 @@ static void parse_event_log_entry(struct

Attached are the patches to support super page with EPT. We only support 2M size. And shadow may still work fine with 4K pages. The patches can be split into 3 parts. Apply order is as attached. tool.diff To allocate 2M physical contiguous memory in guest except the first 2M and the last 2M. The first 2M covers special memory, and Xen use the last few pages in guest memory to do special

This patch adds lost logic for vga initialization. It was lost after changing to new Qemu. Signed-off-by : Kevin Tian <kevin.tian@intel.com> Signed-off-by : Zhang Xiantao <xiantao.zhang@intel.com> Thanks & Best Regards -Xiantao OTC,Intel Corporation _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

Zhang, Xiantao wrote: > Hi Folks, > We are working on enabling KVM support on IA64 platform, and now > Linux, Windows guests get stable run and achieve reasonable performance > on KVM with Open GFW. But you know, the current KVM only considers x86 > platform, and is short of cross-architecture framework. Currently, we > have a proposal for KVM source layout to accommodate new

Zhang, Xiantao wrote: > Hi Folks, > We are working on enabling KVM support on IA64 platform, and now > Linux, Windows guests get stable run and achieve reasonable performance > on KVM with Open GFW. But you know, the current KVM only considers x86 > platform, and is short of cross-architecture framework. Currently, we > have a proposal for KVM source layout to accommodate new

Zhang, Xiantao wrote: >>From 62895ff991d48398a77afdbf7f2bef127e802230 Mon Sep 17 00:00:00 2001 > From: Xiantao Zhang <xiantao.zhang at intel.com> > Date: Fri, 28 Mar 2008 09:49:57 +0800 > Subject: [PATCH] KVM: IA64: Add kvm arch-specific core code for > kvm/ia64. > > kvm_ia64.c is created to handle kvm ia64-specific core logic. > Signed-off-by: Xiantao Zhang

Zhang, Xiantao wrote: >>From 62895ff991d48398a77afdbf7f2bef127e802230 Mon Sep 17 00:00:00 2001 > From: Xiantao Zhang <xiantao.zhang at intel.com> > Date: Fri, 28 Mar 2008 09:49:57 +0800 > Subject: [PATCH] KVM: IA64: Add kvm arch-specific core code for > kvm/ia64. > > kvm_ia64.c is created to handle kvm ia64-specific core logic. > Signed-off-by: Xiantao Zhang

Due to IA64 balloon driver not ready and it depends on max memory value to allocate its memory. So this fix is necessary now. Thanks & Best Regards -Xiantao OTC,Intel Corporation _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

This patch adds the ia64-specific code for new Qemu . In addition, some ia64 patches aren''t checked into xen-unstable.hg, so I reversed the related logic temporarily. Once sync with xen-ia64-unstable.hg, the logic will regain automatically. Thanks & Best Regards -Xiantao OTC,Intel Corporation _______________________________________________ Xen-devel mailing list

I''m interested in monitoring the amount of stack used by a multi-threaded program. I assume ''stackdepth'' built-in would be useful...but not sure. Been through demo''s, ToolKit, and internals..but it''s just not clicking for me yet. Not sure how to measure start/end of stack size dynamically...Anyone know how to break this down? This message posted from