Displaying 9 results from an estimated 9 matches similar to: "[PATCH 4/6] X86: Disable PCID/INVPCID for pv"
2011 Nov 24
0
[PATCH 5/6] X86: Prepare PCID/INVPCID for hvm
X86: Prepare PCID/INVPCID for hvm
This patch is used to prepare exposing PCID/INVPCID features to hvm guest.
The specific exposure result depend on hvm paging mode (hap/shadow), which would be handled at next patch.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r 1b62d4e08880 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Nov 17 23:09:45 2011 +0800
+++
2008 Nov 19
0
[PATCH] support CPUID hypervisor feature bit
See http://lkml.org/lkml/2008/10/1/246 for more context.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Index: 2008-10-27/xen/arch/x86/domain.c
===================================================================
--- 2008-10-27.orig/xen/arch/x86/domain.c 2008-11-11 16:24:48.000000000 +0100
+++ 2008-10-27/xen/arch/x86/domain.c 2008-11-19 10:22:34.000000000 +0100
@@ -1888,6 +1888,8 @@ void
2012 Sep 20
0
[PATCH 3/3] Expose tsc adjust to hvm guest
Expose tsc adjust to hvm guest
Intel latest SDM (17.13.3) release a new MSR
CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported.
This patch expose it to hvm guest.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r a6d12a1bc758 tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Thu Sep 20 00:03:25 2012 +0800
+++ b/tools/libxc/xc_cpufeature.h Thu Sep 20
2007 Aug 09
0
[PATCH] x86/hvm: miscellaneous CPUID handling changes
- use __clear_bit() rather than clear_bit()
- use switch statements instead of long series of if-s
- eliminate pointless casts
(Applies cleanly only on top of the previously sent SVM/EFER patch.)
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Index: 2007-08-08/xen/arch/x86/hvm/hvm.c
===================================================================
---
2011 Nov 24
0
[PATCH 6/6] X86: implement PCID/INVPCID for hvm
X86: implement PCID/INVPCID for hvm
This patch handle PCID/INVPCID for hvm:
For hap hvm, we enable PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID non-root behavior as running natively;
For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root behavior as vmexit.
Signed-off-by: Liu, Jinsong
2012 May 04
3
[BUG 2.6.32.y] Broken PV migration between hosts with different uptime, non-monotonic time?
Hello,
I encountered the following bug when migrating a Linux-2.6.32.54 PV domain on
Xen-3.4.3 between different hosts, whose uptime differs by several minutes (3
hosts, each ~5 minutes apart): When migrating from a host with lower uptime
to a host with higher uptime, the VM looses it''s network connection for some
time and then continues after some minutes (roughly equivalent to the
2019 Mar 30
1
[PATCH 2/5] x86: Convert some slow-path static_cpu_has() callers to boot_cpu_has()
From: Borislav Petkov <bp at suse.de>
Using static_cpu_has() is pointless on those paths, convert them to the
boot_cpu_has() variant.
No functional changes.
Reported-by: Nadav Amit <nadav.amit at gmail.com>
Signed-off-by: Borislav Petkov <bp at suse.de>
Cc: Aubrey Li <aubrey.li at intel.com>
Cc: Dave Hansen <dave.hansen at intel.com>
Cc: Dominik Brodowski <linux
2016 Apr 01
0
[PATCH] devinit/gf100: make devinit on resume safer
In case of successful suspend, devinit will have to be run and this is
the behavior currently hardcoded. However, as FD bug 94725 suggests,
there might be cases where runtime suspend leaves the GPU powered, and
in such cases devinit should not be run on resume.
On GF100+ we have a reliable way to know whether we need to run devinit.
Use it instead of blindly trusting the flag set by
2013 Sep 23
11
[PATCH v4 0/4] x86/HVM: miscellaneous improvements
The first and third patches are cleaned up versions of an earlier v3
submission by Yang.
1: Nested VMX: check VMX capability before read VMX related MSRs
2: VMX: clean up capability checks
3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation
4: x86: make hvm_cpuid() tolerate NULL pointers
Signed-off-by: Jan Beulich <jbeulich@suse.com>