similar to: FPGA encode stages flow diagram

Andrey Fillipov posted the following update at his sourceforge website on 11/16/04. "Coded and simulated the DC predictor module - hope the Theora description I used matches the actual codec :-) Also modified the modules released earlier to support non-coded blocks. For the DCT/IDCT I tried to reduce the power consuption by minimizing switching of the registers and counters when the

Thank, Timothy! I add this stages. About RLE: I have one more unresolved stage. Mike Melanson wrote in "VP3 Bitstream Format..." about RLE using: "* Zigzag Ordering: After transforming and quantizing a block of samples, the samples are not in an optimal order for run length encoding. Zigzag ordering rearranges the samples to put more zeros between non-zero samples." If we pass

Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> =

Hi, Is somewhere alghorithm description of encoder process implemented in libtheora? May be some drafts? May be frame dataflow throw encoder stages? PLEASE -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/theora/attachments/20110318/c3e8e109/attachment.htm

Good day! I'm creating HDL IP CORE (for using in FPGA) for theora encoder (now only I-frames). I don't undestand one moment. Now i develop such stages: 1. From RBG(byer) to YCbCr converter 2. DCT processing (8x8 pixels blocks) 3. Quantizator of DCT coeff. 4. Zig-Zag of quantized DCT coeff. and now i have uresolved last stage of compression - how i must send 8x8 blocks to huffman

Hi, I get strange code when using regalloc=greedy. A value spill is redundant and cleared, as another spill of same value is inserted. The former spill is however not NOP:ed, but KILL:ed, thus the operands get a kill status. The code becomes: %vreg301<def> = mv32Imm 200000000, pred:0, pred:%noreg, %CCReg<imp-def,dead>, %ac0<imp-use>, %ac1<imp-use>; aN32_0_7:%vreg301

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I would like to propose an interface change/extension, in order to be able to clearly differ from a PRE_SEND and a POST_RECEIVE item_t->preprocess-ing calls. IMHO there is no option to differ from item->preprocess(..), called from [1] and called from [2], at the moment. My idea is to extend the item_t->preprocess(..) with an additional

---------- Forwarded message ---------- From: digital design <developer.fpga at gmail.com> Date: 21 March 2011 13:38 Subject: Re: [theora] alghorithm of working encoder in libtheora To: bens at alum.mit.edu Cc: Reply-All at xiph.org On 18 March 2011 23:15, Benjamin M. Schwartz <bmschwar at fas.harvard.edu>wrote: > On 03/18/2011 01:44 PM, digital design wrote: > > Now i

Hi, We would like to use the OPUS codec @ 16 kHz sampling rate and max 32 kbps. What about implementing an OPUS coder and decoder in an FPGA? Has this been done? Would either coder or decoder more suitable for FPGA implementation? Best regards Fredrik Bonde -------------- next part -------------- An HTML attachment was scrubbed... URL:

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the

Hi LLVM community members. I downloaded LLVM-GCC4.2 Front-end source code and succefully installed alongwith LLVM-2.3 on linux x86_64. I think it's front-end has better optimizations. I am naive to LLVM environment, my focus is to generate LLVM inermediate code for FPGA. Are there any resources/links/papers/documents which discusses LLVM intermediate generation for FPGA needs. I am aware

<https://lh4.googleusercontent.com/-IA0TutFw54A/UmVnJwi7CHI/AAAAAAAAAzg/fEZFf_kHsug/s1600/git.gif> Hi again, I''m working on http://ruby.railstutorial.org section http://ruby.railstutorial.org/ruby-on-rails-tutorial-book#sec-git_push I''m trying to push the repository to the remote site but what ever I fials. I''ve updated, removed the s of the https etc but still

Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled

i was just writing this: http://www.gp32x.com/board/index.php?/topic/60228-replicating-the-success-of-the-openpandora-discussion-v20/ when something that just occurred to me, half way through, and i would greatly appreciate some help evaluating whether it's feasible. put these together: http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm

Luke Kenneth Casson Leighton wrote: > i was just writing this: > http://www.gp32x.com/board/index.php?/topic/60228-replicating-the-success-of-the-openpandora-discussion-v20/ > > when something that just occurred to me, half way through, and i would > greatly appreciate some help evaluating whether it's feasible. > > put these together: >

On Sun, Aug 21, 2011 at 12:48 AM, Nick Lewycky <nicholas at mxc.ca> wrote: > The way in which Gallium3D targets LLVM, is that it waits until it receives > the shader program from the application, then compiles that down to LLVM IR. > That's too late to start synthesizing hardware (unless you're planning to > ship an FPGA as the graphics card, in which case reprogramming

Hi all, Great news. On Thursday I finally play a video on FPGA. As I said the implementation is using the NIOS II processor. Andr? Costa is hard working to use the LEON processor. The video resolution is 96x80, because we have some FPGA internal memory constraints. I will try to use external memory to make possible decode a video of at least 320x240. The result can be see here: