similar to: Theora playing on a FPGA

Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled

Hi, I did some improvements and some bug corrections in Theora FPGA code. I'd like to post this new version in the SVN. How can I do that? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

What is the PostProcessingLevel field of PB_INSTANCE? When is it used? It is used for all Theora's video or it is just for legacy support with VP3? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

Hi all, Does Theora Community have an interest in a multi-thread decoder implementation? I'm starting to work with multi-thread and I thought that Theora Decoder is a good choice for me, because I had been working with it in a FPGA implementation and I have experience with the library. I'm thinking in working with LoopFilter at first. Do you think I could start with it or there is a

Hi all, I have to compare the theora codec with MPEG and H264. I was googling and I found that the PSNR is a common used parameter. How can I do this with Theora? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

Hi all, I apologize to not keep you up to date to what is going on with my project. Portavales has worked in a desk behind me and when we go to take coffee we talk about the project. Second I didn't know we have to discuss weekly, it was my fault. I should have read the rules. Sorry. At the first month, I studied the code and the Theora Beta implementation. The code is completely different

I have tried to add a plunging to the "libtheora-1.0beta2" (network bandwidth measuring component was added) and Got it success for some far now the problem is when it is added the encoding process get extremely slow (around 20 seconds delay). I think that the problem is with my modified Makefile (some flag may have missed). the following is my modified Makefile.am which is in the

Shows that as the MCU increases, the OpenMP extra overhead is amortized and OpenMP becomes as fast as the pthreads implementation. The last chart http://lampiao.lsc.ic.unicamp.br/~piga/gsoc_2008/systime.png Shows that both pthreads and OpenMP overhead decreases as what seems to be a logarithmic function of the MCU size. This was a great experiment, and from what I can conclude, the OpenMP

Hi, This email is to inform what I have been doing since the mid-term. After the mid-term I worked on a pipeline implementation with OpenMP. As I said before I did a pipelined implementation of these functions: (c_dec_dc_unpredict_mcu_plane + oc_dec_frags_recon_mcu_plane) and (oc_state_loop_filter_frag_rows + oc_state_borders_fill_rows) as explained in my previous email. But the results were

Hello, First of all, I would like to say that my work that I wrote in the other email would be to do in hardware the functions: CopyRecon, LoopFilter and UpdateUMVBorder. These are modules that Leonardo had made, but it wasn't ok in FPGA. When I had a chat with Leonardo we were thinking in rewrite these module for to do this running in FPGA (to debug in a Hardware level is much more

I have tried to add a plunging to the "libtheora-1.0beta2" (network bandwidth measuring component was added) and Got it success for some far now the problem is when it is added the encoding process get extremely slow (around 20 seconds delay). I think that the problem is with my modified Makefile (some flag may have missed). the following is my modified Makefile.am which is in the

I'm trying to implement the dct_decoder's LoopFilter function in a FPGA. I need to know what is the maximum memory allocation size which display_fragment and recon_pixel_index_table points. These are fields of PB_INSTANCE structure that is declared in the codec_internal.h Thank you =========================== Leonardo de Paula Rosa Piga Computer Engineering Student Universidade

Hello, I 've just spent some trouble in tryng to fix archive attribute. At thi time a samba user different from the owner of a file can't set or unset the archive attribute from a Windows Client. Anyone know how to fix it? Please help me, It's a long time that the backup is unavailable and a hardware failure of the HD is coming....I'm sure... Bye, Carlo Piga

Hello people My name is Felipe and I sent a proposal to the Google Summer of Code that the goal is to get a FPGA embeded system decoding Theora Streams in real-time. It was accepted and the mentor is the Ralph Giles. The proposal can be viewd here: http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt There is also a presentation with a better division of the

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

Hi LLVM community members. I downloaded LLVM-GCC4.2 Front-end source code and succefully installed alongwith LLVM-2.3 on linux x86_64. I think it's front-end has better optimizations. I am naive to LLVM environment, my focus is to generate LLVM inermediate code for FPGA. Are there any resources/links/papers/documents which discusses LLVM intermediate generation for FPGA needs. I am aware

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

Hi, We would like to use the OPUS codec @ 16 kHz sampling rate and max 32 kbps. What about implementing an OPUS coder and decoder in an FPGA? Has this been done? Would either coder or decoder more suitable for FPGA implementation? Best regards Fredrik Bonde -------------- next part -------------- An HTML attachment was scrubbed... URL:

Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the