Displaying 20 results from an estimated 700 matches similar to: "implementation in hardware"
2005 Mar 08
6
FPGA implementation/ players speed?
Today I've got first video clips made by the camera and compressed "on the
fly" - 1280x1024x30fps. Image quality is far from perfect - I don't have
yet any way to preview images, and a single acquisition still requires a
bunch of commands. So I'm really close to have a camera that will be able
to serve the Ogg/Theora streams, now but will it be possible to play it on
a PC? I
2004 Sep 07
3
FPGA implementation in the camera
I'm considering implementing the Theora format in the FPGA of the new
camera. The previous model (Elphel 313 - http://www.elphel.com,
https://sourceforge.net/projects/elphel) had smaller FPGA and was
able to produce just motion JPEG utilizing 97% of the resources. The
new (model 333) camera uses 3 times bigger FPGA (and also faster), it
also has increased frame buffer and system memory.
2004 Sep 07
3
FPGA implementation in the camera
I'm considering implementing the Theora format in the FPGA of the new
camera. The previous model (Elphel 313 - http://www.elphel.com,
https://sourceforge.net/projects/elphel) had smaller FPGA and was
able to produce just motion JPEG utilizing 97% of the resources. The
new (model 333) camera uses 3 times bigger FPGA (and also faster), it
also has increased frame buffer and system memory.
2021 Dec 02
1
NHW Project development
Raphael,
Some 15 years ago I implemented limited functionality Theora in our cameras FPGA (it took me 6 month of hard labor), and then gave up - it is a very crowded space and it is difficult to compete with more advanced codecs. And for our other work we anyway need almost raw image data, so we are using JPEG-based JP4 format (https://community.elphel.com/jp4) that we originally developed for
2011 Mar 22
0
FPGA implementation in the camera
Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey
describe encoder structure, this like:
"I see the following structure of the compressor implemented in the FPGA
(Xilinx Spartan 3 1000K gates):
1. Data from the external frame buffer (FB) memory goes to the
Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6
8x8 blocks (one macroblock) on the
2021 Dec 02
1
NHW Project development
Hi Andrey,
Thank you for your answer.Actually, NHW is very low-power so I think it
could be geared toward any hardware.But actually I don't have hardware
skills, so NHW is not a real hardware project for now maybe? I agree with
you that it is extremely difficult (for me) to build a community around
NHW, I'm certainly very bad/underskilled at it.Any help is welcome!
Cheers,
Raphael
Le
2008 Feb 01
6
Dynamic Change Parameters..
I am going to improve theora codec with dynamically changing way. In this
case we want to change compression parameters like video_q, sharpness when a
keyframe is generated. When i set video quality parameter using cpi->
pb.info.quality in CommpressKeyFrame in encoder_toplevel it will not change
dynamically. Can you please help me to do this. Wich function should i cange
to achieve my
2005 Feb 11
1
Changing the IDCT spec
So, in preparation for some decoder optimization work planned by Rudolf
Marek, the subject of the size of the registers needed in the IDCT
came up.
The current spec language ensures that the result is exactly compatible
with the C code for VP3. This language requires that some of the
arguments to the multiplies be 17 or 18 bits, because they need to hold
the sum or difference of two 16-bit
2004 Nov 17
4
FPGA implementation
Andrey Fillipov posted the following update at his sourceforge website on
11/16/04.
"Coded and simulated the DC predictor module - hope the Theora description I
used matches the actual codec :-)
Also modified the modules released earlier to support non-coded blocks. For
the DCT/IDCT I tried to reduce the power consuption by minimizing switching
of the registers and counters when the
2006 Jul 02
5
What goes to Hardware ?
Hi people,
As I said before: I did the IDCT to run on the FPGA.
My friends from university did the Reconstruction routines running on the FPGA.
I'm helping with the LoopFilter, and it is almost there.
(all VHDL)
I did a small profiling of the libTheora running on a Altera Stratix II device:
The processor used was the NIOS II with 8Kb of data and instruction
cache, branch prediction and
2010 May 14
1
Elphel's JP4
Hi,
just a small follow up of recent discussions about Elphel's JP4 format.
I'm working with Andrey and fellows from Elphel to improve support for
JP4 format in the context of Elphel's Apertus project
(http://www.apert.us). As posted by Basil, on
http://wiki.elphel.com/index.php?title=JP4 there is plenty of
information about the format and how to post process it to get back
your real
2008 Aug 15
6
handheld theora video camera wish list
What would your wish list be for a handheld theora
video camera?
640x480 25fps/30fps
320x240 25fps/30fps
Record to a memory card (SD)
Lan / WIFI support (auto/manual upload of file on
memory card)
Live streaming (icecast like)
Videoconferencing support
Voip (sip) speex audio
I am bouncing the idea around of developing a handheld
video camera
designed for mobile video streaming
Win a
2005 Apr 03
0
Re: Theora cameras
Andrey and I were having a conversation off list, forwarding relevent
bits of the last response from Andrey for public reference.
--- begin forward ---
On Mar 31, 2005 9:22 PM, Ralph Giles <giles@xiph.org> wrote:
> On Thu, Mar 31, 2005 at 06:46:06PM -0700, Andrey Filippov wrote:
>
> > > BTW, you asked about padding theora packet data to a byte boundary. I
> > >
2010 May 18
2
idct8x8 C version in libtheora1.1 release
When using the IDCT routines, the C version [ lib/idct.c:
oc_idct8x8_c(ogg_int16_t _y[64],int _last_zzi)] in libtheora 1.1.1, the
decoded image is garbled. Is it functionally equivalent to the MMX optimized
version [lib/x86/mmxidct.c: oc_idct8x8_mmx(ogg_int16_t _y[64],int
_last_zzi)] ?
I used some of the Theora video files from here:
http://wiki.xiph.org/index.php/List_of_Theora_videos for
2011 Mar 28
1
idct/fdct.c function calls
Hi.
I am trying to find calls of idct/fdct.c functions by tracing png2theora.c calls.
But found only:
analyze.c:oc_dct_cost2()
Where and when idct/fdct/mmxidct/mmxfdct.c functions are used?
Mentions of "dct" word:
====
pacify at optima-amd64:/usr/src/libtheora-1.2.0alpha1/lib$ grep dct *.c | cut -f1 -d":" | uniq -c
???? 19 analyze.c
???? 28 decode.c
???? 22 encode.c
????? 4
2005 Jul 20
1
MMX IDCT for theora-exp
Hello,
I'm attaching IDCT MMX patch. I reused IDCT from theora-a3-MMXd.zip.
It should work on 64bit X86 platform too.
Here is most used functions when playing video with jet aircrafts (gripen)
Ogg logical stream 310b2968 is Theora 720x480 29.97 fps video
Encoded frame content is 720x480 with 0x0 offset
I can play this video with like 200-300 frame drops on Athlon XP 1700+
CPU load (with
2004 Oct 29
2
Fwd: RE: DSP stamp
Are we interested, or ready for this? Andrew Seddon is offering to provide
hardware to port Theora to the DSP Stamp.
http://www.linuxdevices.com/news/NS4405077268.html
John
---------- Forwarded Message ----------
Subject: RE: DSP stamp
Date: Friday 29 October 2004 03:50 am
From: "Andrew Seddon" <andrew.seddon@camsig.co.uk>
To: "'John Kintree'"
2003 Mar 05
5
VP3 IDCT
Hi,
Is there anything special I need to know about VP3's IDCT? I mean
besides the fact that there are separate IDCTs to handle sparse
coefficient matrices. Are the IDCT functions mathematically equivalent to
any textbook IDCT functions?
Thanks...
--
-Mike Melanson
--- >8 ----
List archives: http://www.xiph.org/archives/
Ogg project homepage: http://www.xiph.org/ogg/
To
2004 Oct 28
1
Re: DSP stamp
Yes, the Theora codec is based on VP3, which is an earlier version of ON2's
VP6 codec. Theora is currently at its alpha 3 release, and is stable enough
to have been used already for streaming live video from a number of
conferences, and for encoding several videos that can be found at
www.theora.org.
Development has progressed to the point that the value of the codec can be
seen. That
2008 Mar 07
1
Bug in reference idct.
Hi
The Theora specification states, in section 7.9.3 ("The 1D Inverse DCT")
steps 14-16:
14. Assign T[5] the value T[4] - T[5].
15. Truncate T[5] to a 16-bit representation by dropping any higher-order
bits.
16. Assign T[5] the value C4 * (-T[5]) >> 16.
However, the relevant section of code in the reference decoder
(lib/dec/idct.c line 50) is: