similar to: Chip

Hi, does anyone have small programms in C, one to encode and one to decode with celt, that I could use for a fpga chip softcore? greets yon -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/opus/attachments/20100819/7cd96a41/attachment-0002.htm

Background: OS: Linux Mandrake 10.1 release: R 2.0.0 editor: GNU Emacs 21.3.2 front-end: ESS 5.2.3 --------------------------------- Colleagues Is there a function in R that is an equivalent of zoom in matlab? This is very useful for being able to magnify details in a plot. I have searched the help for "zoom", "interactive zooming", and "magnify". The R search

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, all ! I'm trying to add users to my NT domain from my samba servers (This to create all my accounts with only a single script, I do not want to create them on the PDC, then create their folders on the samba file server with another...) I managed to create account with "net rpc user add", then put them in the right domain

Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This

Dear R-devel, A couple of weeks ago I started to use the R C API for package development. Without knowing much about C, I've been able to write some routines sucessfully... until now. My problem consists in dynamically creating a list ("L1") of lists using .Call, the tricky part is that each element of the "mother list" contains two vectors (INTSXP and REALEXP types) with

Hello, my name is Axel Reimer and I am new to this mailing list. I subscribed because I was just thinking about how hard it would be to implement a flac-decoder in VHDL (in order to use it on a Xilinx-FPGA). Since I am working at a University in Germany I was thinking of offering this project for students. What do you think. How much time would you suggest for such an implementation (if only

Hi all, Just a stupid question The IDctSlow function on file idct.c has this line : ip[0] = (ogg_int16_t)((_Gd + _Cd ) >> 0); The ip[0] , _Gd and _Cd are of type ogg_int32_t My question is: The result of (_Gd + _Cd) can be a number with more than 16 bits ? (yes, it can be because they are int32, but the algorithm could guarantee something about that... I dont know...) If

To All,     Has anyone worked with generating vhdl code to promela script for the spin model checker??   David Blubaugh         -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121204/b76bd607/attachment.html>

The time has come to review the current Contributor and Core contributor grants for ZFS. Since all of the ZFS core contributors grants are set to expire on 02-24-2009 we need to renew the members that are still contributing at core contributor levels. We should also add some new members to both Contributor and Core contributor levels. First the current list of Core contributors: Bill

I don't have a solution for you, but when you found one or start the project on your own, let me know. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111002/f54dd8de/attachment.html>

Hi everyone, I?m a graduate student in a Brazilian Intitute of Technology, and I?m doing some academic research regarding secure voice transmission over phone lines. One of our reserach goals is to implement a hardware vocoder, with low bit rates, and a preferably free algorithm, to be used in this secure voice system. Actually, there is a functional system using a proprietary AMBE

Summary: If you use ZFS, do not downgrade from build 35 or later to build 34 or earlier. This putback (into Solaris Nevada build 35) introduced a backwards- compatable change to the ZFS on-disk format. Old pools will be seamlessly accessed by the new code; you do not need to do anything special. However, do *not* downgrade from build 35 or later to build 34 or earlier. If you do so, some of

On 30.8.2011, at 19.19, Eli Friedman wrote: > reg2mem won't do quite this transformation... not sure exactly what you need. I need to get rid of phis. This code is compiled from C++ and for some functions there are no phis, but multiple call instructions. I am targeting hardware in the end, and the next tool reading the IR does not like phis when it's generating VHDL. My questions may

I'm considering creating an ogg vorbis decoder chip for my senior project in school. At this point, my idea is to have a program (such as XMMS, ogg123, WinAMP) send the encoded ogg bitstream through a USB port to my project, which is then decoded. My project then returns the raw PCM audio, which is then handled by the player program for final audio output. I'm planning on USB as it

On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis

Dear r-helpers, we have installation problems: Successful installation of R-0.63 base package on Solaris 2.5.1 with the SunSoft compilers f77, c version 4.2. We habe problems with the installation of further packages e.g. integrate from CRAN. R code works but the shared objects built from fortran code do not find the appropriate libs with functions like __pow_ii or __epx at runtime. We tried

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never

The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm

I''m playing around with snv_128 on one of my systems, and trying to see what kinda of benefits enabling dedup will give me. The standard practice for reprocessing data that''s already stored to add compression and now dedup seems to be a send / receive pipe similar to: zfs send -R <old fs>@snap | zfs recv -d <new fs> However, according to the man page,

Hey! I was wondering if active-HDL (VHDL simulator) will work with WINE 1.0? active-HDL (i regret to say) is only for windows.... :( Thanks :)