similar to: [RFC PATCH 5/5] drm/nouveau: gpu lockup recovery

Overall idea: Detect lockups by watching for timeouts (vm flush / fence), return -EIOs, handle them at ioctl level, reset the GPU and repeat last ioctl. GPU reset is done by doing suspend / resume cycle with few tweaks: - CPU-only bo eviction - ignoring vm flush / fence timeouts - shortening waits Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> ---

Nouveau, in normal circumstances, does not need device lock for every ioctl, but incoming "gpu reset" code needs exclusive access to the device. This commit adds drm_driver flag which turns on read lock ioctl encapsulation. Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- drivers/gpu/drm/drm_drv.c | 6 ++++++ drivers/gpu/drm/drm_stub.c | 2 ++

Fence lock needs to be initialized before any call to nouveau_channel_put because it calls nouveau_channel_idle->nouveau_fence_update which uses fence lock. BUG: spinlock bad magic on CPU#0, test/24134 lock: ffff88019f90dba8, .magic: 00000000, .owner: <none>/-1, .owner_cpu: 0 Pid: 24134, comm: test Not tainted 3.0.0-nv+ #800 Call Trace: spin_bug+0x9c/0xa3 do_raw_spin_lock+0x29/0x13c

This removes dependence on external firmware for NV50 generation cards. If the generated ctxprogs don't work for you for some reason, please report it. Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/Makefile | 2 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 1 + drivers/gpu/drm/nouveau/nv50_graph.c | 74 +-

- 'joi' on irc pointed out that this triggers a BUG_ON, because kzalloc could sleep. - The irq handler should restore the value NV03_PFIFO_CACHES, but still it's better if this stuff doesn't happen in the middle of fifo create context. I see no reason in spin locking pgraph create context, it isn't activated at that stage. - Move and rename the lock after some discussion with

Dynamically resizing the framebuffer on nv04 was like playing Russian roulette (and it often happened gratuitously) because it seems unable to scan out from buffers above 16MB. This patch splits the mappable VRAM into two chunks when that's the case, and makes the higher one to be used as well when applicable. Signed-off-by: Francisco Jerez <currojerez at riseup.net> ---

- Use the "direct" objects that previously only the kernel fifo had. - This avoids corruption on some buffer moves. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 23 ++--------------- drivers/gpu/drm/nouveau/nouveau_object.c | 36 ++++++++++++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_state.c | 38

Useful for simulating low-mem cards. Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_drv.c | 4 ++++ drivers/gpu/drm/nouveau/nouveau_drv.h | 2 ++ drivers/gpu/drm/nouveau/nouveau_mem.c | 16 ++++++++++++++++ drivers/gpu/drm/nouveau/nv50_vram.c | 1 + drivers/gpu/drm/nouveau/nvc0_vram.c | 1 + 5 files changed, 24

Remove drm_nouveau_private::fb member and map the piece of VRAM only when accessing VGA fonts. Collect copied code into the static function nouveau_vga_font_io(). Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_drv.h | 17 ------- drivers/gpu/drm/nouveau/nouveau_hw.c | 75 +++++++++++++++---------------- drivers/gpu/drm/nouveau/nouveau_state.c |

Hi This does not look right: diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 775a701..c1fd42b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -540,7 +540,8 @@ nouveau_mem_detect(struct drm_device *dev) dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA); dev_priv->vram_size &=

Several nvidia-based systems don't support backlight control via the standard ACPI control mechanisms. Instead, it's necessary for the driver to modify the backlight control registers directly. This patch adds support for determining whether the registers appear to be in use, and if so registers a kernel backlight device to control them. The backlight can then be controlled via

This adds basic support for driving sensor chips off the nvidia i2c buses, along with basic support for reading the internal GPU sensor on supported chipsets. It's heavily cribbed off nvclock. Having scanned a large number of bioses, I'm pretty convinced that the appropriate i2c bus is always number 2 in the list on <g80 - I'm not sure about later cards yet. There's still a lot

From: Pekka Enberg <penberg at cs.helsinki.fi> Convert the macros in nouveau_mem_alloc() to nouveau_mem_alloc_agp(), nouveau_mem_alloc_fb(), and nouveau_mem_alloc_pci() functions that use a new generic __nouveau_mem_alloc() function to allocate and map memory. Signed-off-by: Pekka Enberg <penberg at cs.helsinki.fi> --- shared-core/nouveau_mem.c | 174

Allow the software channel to be created now, since methods for vblanking have been implemented. The instmem flush seems to be needed on fermi to prevent a race, but I enabled it on earlier cards too since they seem to be susceptible to the same race. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 9 ----

Compiled, tested. Look ok. -- Jabber/XMPP: okias at isgeek.info SIP VoIP: sip:17474537254 at proxy01.sipphone.com -------------- next part -------------- This patch remove leftover from UMS. Signed-off-by: David Heidelberger <d.okias at gmail.com> --- diff -Naur a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c --- a/drivers/gpu/drm/nouveau/nouveau_dma.c

Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/nv50_grctx.c | 13 ++++++++++++- 1 files changed, 12 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index 3c3cc46..42a8fb2 100644 --- a/drivers/gpu/drm/nouveau/nv50_grctx.c +++ b/drivers/gpu/drm/nouveau/nv50_grctx.c @@ -177,6 +177,7

Only one type was ever used. This is needed to simplify the fence support in the next commit. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c | 5 +-- drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 1 - drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 14 ++------- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 50

--- drivers/gpu/drm/nouveau/nouveau_state.c | 52 ++++++++++++++++--------------- 1 files changed, 27 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 2ed41d3..25d207c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -317,7 +317,7 @@ nouveau_card_init(struct

--- drivers/gpu/drm/nouveau/nouveau_state.c | 73 ++++++++++++++++++++----------- 1 files changed, 48 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 2ed41d3..9fc5824 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -317,7 +317,7 @@ nouveau_card_init(struct

Currently, we take down the sgdma engine without evicting all buffers from VRAM. The TTM device release will try to evict anything in VRAM to GART memory, but this will fail since sgdma has already been taken down. This causes an infinite loop in kernel mode on module unload. It usually doesn't happen because there aren't any buffer on close. However, if the GPU is locked up, this