similar to: (no subject)

--- rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml index 500cea9..e006dbe 100644 --- a/rnndb/memory/nvc0_pbfb.xml +++ b/rnndb/memory/nvc0_pbfb.xml @@ -49,23 +49,54 @@ Most bitfields are unknown. </doc> <bitfield high="7"

This patchset applies some minor fixes to renouveau.xml and then unifies the nv30 and nv40 register definitions. nv30 and nv40 are very similar and have the same offsets for the registers they share. The major differences are: 1. Texture setup is different due to full NPOT support on nv40 2. More advanced blending/render targets on nv40 3. NV30 has fixed function registers, which NV40 lacks The

NV10TCL defines the vertex buffer registers both as arrays and as individual named registers. This causes duplicate register definitions and the individual registers are not used either by the DDX or by the Mesa driver. Francisco Jerez said to remove them all. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> --- renouveau.xml | 49

First some data errors I get with both nv20 exa and nv20 dri/mesa. 1. RT_FORMAT LINEAR + X8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000105 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000105 LINEAR + A8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000108 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000108 The only value I found in renouveau dump

On Fri, Oct 9, 2020 at 5:54 PM Karol Herbst <kherbst at redhat.com> wrote: > > On Fri, Oct 9, 2020 at 11:35 PM Ondrej Zary <linux at zary.sk> wrote: > > > > Hello, > > I'm testing 5.9.0-rc8 and found that Riva TNT2 stopped working: > > [ 0.000000] Linux version 5.9.0-rc8+ (zary at gsql) (gcc (Debian 8.3.0-6) 8.3.0, GNU ld (GNU Binutils for Debian)

Hello, I've recently come across an error reported by the GPU and would like to know what it means and especially what causes it to be triggered. Any information would be very useful: I'm seeing MP warp error 0x10 (appears in MP register 0x48). This is what we currently have in nouveau: <reg32 offset="0x048" name="TRAP_WARP_ERROR"> <!-- ctx-switched -->

On Fri, Nov 17, 2017 at 2:37 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Fri, Nov 17, 2017 at 2:25 PM, Ondrej Zary <linux at rainbow-software.org> wrote: >> On Friday 17 November 2017 18:41:17 Ilia Mirkin wrote: >>> On Fri, Nov 17, 2017 at 12:33 PM, Ondrej Zary >>> >>> <linux at rainbow-software.org> wrote: >>> > @@ -483,8

On 03/02/2018 11:29 PM, Ilia Mirkin wrote: > On Fri, Mar 2, 2018 at 5:16 PM, Mario Kleiner > <mario.kleiner.de at gmail.com> wrote: >> On 03/01/2018 07:21 PM, nouveau-request at lists.freedesktop.org wrote: >>> >>> >>> Message: 1 >>> Date: Thu, 1 Mar 2018 08:15:55 -0500 >>> From: Ilia Mirkin <imirkin at alum.mit.edu> >>>

On Wed, Feb 07, 2018 at 06:28:42PM +0200, Ville Syrjälä wrote: > On Sun, Feb 04, 2018 at 06:50:45PM -0500, Ilia Mirkin wrote: > > In case anyone's curious about 30bpp framebuffer support, here's the > > current status: > > > > Kernel: > > > > Ben and I have switched the code to using a 256-based LUT for Kepler+, > > and I've also written a

Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> =

Hi Robert, Thanks for the quick response! That goes in line with my observations which is that these things happen when using an ATOM/RED instruction. I've checked and rechecked that I'm generating ops with identical bits as what the proprietary driver does, however (and nvdisasm prints identical output). Could you advise what the proper way of indicating that the memory is

Chris Lattner wrote: > On Thu, 2 Dec 2004, Brent Monroe wrote: > >>I'm trying to add the xadd instruction to the X86 back end. >>xadd r/m32, r32 >>exchanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to

Hello, I'm testing 5.9.0-rc8 and found that Riva TNT2 stopped working: [ 0.000000] Linux version 5.9.0-rc8+ (zary at gsql) (gcc (Debian 8.3.0-6) 8.3.0, GNU ld (GNU Binutils for Debian) 2.31.1) #326 SMP Fri Oct 9 22:31:40 CEST 2020 ... [ 14.771464] nouveau 0000:01:00.0: GPU not supported on big-endian [ 14.771782] nouveau: probe of 0000:01:00.0 failed with error -38 big-endian? WTF? The

On Friday 17 November 2017 18:41:17 Ilia Mirkin wrote: > On Fri, Nov 17, 2017 at 12:33 PM, Ondrej Zary > > <linux at rainbow-software.org> wrote: > > @@ -483,8 +483,8 @@ > > nouveau 0000:02:00.0: disp: 0860: 00000000 -> 00000500 > > nouveau 0000:02:00.0: disp: 0864: 00000000 > > nouveau 0000:02:00.0: disp: 0868: 00000000 -> 04000500 >

Thanks Steve, I will try this out. I hadn’t realised that TableGen was restricted to matching instructions with more than one output operand. I’m assuming that this is only a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though):

Thanks again for your help Steve, I’m thinking perhaps my “SelectADDRrr” pattern is inadequate. The sign-extension is at the hardware level, the code generator sees (should see) it as a 16-bit signed register value. My implementation is just: bool SHAVEISelDAGtoDAG::SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset) { if ((Addr.getOpcode() == ISD::ADD) { Base

Dear R list As suggested by Prof Brian Ripley, I have tried to read acf literature. The main problem is I am not the statistician and hence have some problem in understanding the concepts immediately. I came across one literature (http://www.stat.nus.edu.sg/~staxyc/REG32.pdf) on auto-correlation giving the methodology. As per that literature, the auto-correlation is arrived at as per following.

https://bugs.freedesktop.org/show_bug.cgi?id=70390 Priority: medium Bug ID: 70390 Assignee: nouveau at lists.freedesktop.org Summary: G84: Repeated system crashes under graphics load, E[PFIFO] DMA_PUSHER and lots of E[PGRAPH] QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified

--- rnndb/display/nv3_pramdac.xml | 67 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/rnndb/display/nv3_pramdac.xml b/rnndb/display/nv3_pramdac.xml index 13b6a7b..e236921 100644 --- a/rnndb/display/nv3_pramdac.xml +++ b/rnndb/display/nv3_pramdac.xml @@ -79,12 +79,79 @@ <bitfield pos="28" name="VCLK_DB2"/> <bitfield

On 25/08/2014 20:58, Christian Costa wrote: > --- > rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++--- > 1 file changed, 34 insertions(+), 3 deletions(-) > > diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml > index 500cea9..e006dbe 100644 > --- a/rnndb/memory/nvc0_pbfb.xml > +++ b/rnndb/memory/nvc0_pbfb.xml > @@ -49,23 +49,54 @@