similar to: [PATCH 2/2 V2] drm/nv50: Improve PGRAPH interrupt handling.

This will fix races between generated ctxprogs and interrupt handler. Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/nv50_grctx.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index d105fcd..9f909ab 100644 ---

On Thu, Jan 16, 2014 at 1:13 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > > I made the assumption that showing the address is generally useful. Worst > case, it won't make sense but still be displayed. Seems simpler than > special-casing things. Erm, I have a better version of this coming that

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- I made the assumption that showing the address is generally useful. Worst case, it won't make sense but still be displayed. Seems simpler than special-casing things. drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | 117 ++++++++++++----------- 1 file changed, 63 insertions(+), 54 deletions(-) diff --git

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Statuses derived from envytools, as usual. Not 100% sure about the "any" thing, but it makes sense... drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c

Currently Nouveau is unable to dismiss DMA_VTX_PROTECTION errors, which results in an infinite loop in the interrupt handler. These errors are caused both by bugs in the Gallium driver and by user-specified index buffers with out of bounds indices. By mmio-tracing the nVidia drivers, I found out how this is done. On DMA_VTX_PROTECTION, The nVidia driver reads the register 0x402000, always

Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | 174 ++++++++++++------------ 1 file changed, 88 insertions(+), 86 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c index 2fe14da3..76944c4 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c

Hi Deepak, There's... a lot of stuff going on here. Can you describe the goal of this patch (which could then be used as the patch commit message)? The current one basically boils down to "Add support for loading PMU", but merely loading the fw into a fuc engine is just a handful lines of code. Also, except in rare cases, it's customary to split up patches of this size into

On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > These chipsets include the VP2 engine which is composed of a bitstream > processor (BSP) that decodes H.264 and a video processor (VP) which can > do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are > driven by separate xtensa chips embedded in the hardware. This patch > provides the

Hi Mirkin, Your observations are quiet correct. After the boot code is submitted successfully, I will submit the code to configure & enable features of PMU.(This will be done by sending cmds to PMU). Now talking about this patch: Apart from just the boot code, I have also included some things in this patch that I can remove for now(I will include these things in later digestible chunks): -

Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nouveau_drv.h | 23 +++++ drivers/gpu/drm/nouveau/nouveau_reg.h | 16 ++-- drivers/gpu/drm/nouveau/nouveau_state.c | 8 ++ drivers/gpu/drm/nouveau/nv10_fb.c | 32 ++++++-- drivers/gpu/drm/nouveau/nv10_graph.c | 47 ++++++++--- drivers/gpu/drm/nouveau/nv20_graph.c | 80

On Wed, Nov 1, 2017 at 12:51 PM, Karol Herbst <kherbst at redhat.com> wrote: > fixes compilation issues with recent envytools, because movw was removed > from fuc5, because it doesn't exist there anymore. The current code is > most likely broken for fuc5 hardware as well and might have triggered all > kinds of random memory reclocking fails. > > Changes in fuc3 binaries

Since the original merge of nouveau to upstream kernel, we were assuming that nv90 (and later) cards have 32 lines. Based on mmio traces of the binary driver, as well as PBUS error messages during read/write of the e070/e074 registers, we can conclude that nv92 has only 16 lines whereas nv94 (and later) cards have 32. Reported-and-tested-by: David M. Lloyd <david.lloyd at redhat.com>

Add support for reclocking on GK20A, using a statically-defined pstates table. The algorithms for calculating the coefficients and setting the clocks are directly taken from the ChromeOS kernel. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 1 +

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 2 + drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | 16 ++ drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | 318 +++++++++++++++++++-- .../gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc | 111 +++++++ drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h | 5 +

Add support for initializing the priv ring of GK20A. This is done by the BIOS on desktop GPUs, but needs to be done by hand on Tegra. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1 + drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c | 108

v2: Check for PFIFO, don't pause if it's not yet running. This should fix reclocking on boot Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 4 +- .../gpu/drm/nouveau/core/include/subdev/clock.h | 4 + drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c | 439

v2: Check for PFIFO, don't pause if it's not yet running. This should fix reclocking on boot v3: Tiny clean up Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 4 +- .../gpu/drm/nouveau/core/include/subdev/clock.h | 4 +

The various register access wrappers in nouveau_hw.h are so noisy when drm.debug > 0, that some of them can overflow the kernel message buffer. Add nouveau.ko parameter 'reg_debug', a bitmask that enables each of the wrapper debug messages individually. By default, nothing is printed. Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_drv.c | 6

On 13 April 2015 at 20:42, Alexandre Courbot <acourbot at nvidia.com> wrote: > Ben, I guess our main remaining concern with this patch is how it should > integrate wrt. the existing PMU code. Since it is designed to interact with > the NVIDIA firmware, maybe we should use a different base code, or do you > think we can somehow share code and data structures? Hey Alexandre, Sorry

It adds PMU boot support.It loads PMU firmware into PMU falcon.RM/Kernel driver receives INIT ack (through interrupt mechanism) from PMU when PMU boots with success. Signed-off-by: Deepak Goyal <dgoyal at nvidia.com> --- drm/nouveau/include/nvkm/subdev/pmu.h | 26 +- drm/nouveau/nvkm/subdev/pmu/base.c | 108 ++ drm/nouveau/nvkm/subdev/pmu/gk20a.c | 2131