similar to: Windows domain clients can't connect to samba share

Solution is really simple. Since this server is dual-homed ( 2 nic's ), i suggest setup advanced routing tables. The short version of howto setup. edit /etc/iproute2/rt_tables and Add : 10 OfficeLan 20 InternetWan Lookup the routing tables: ip route show table OfficeLan ip route show table InternetWan The default gateway's is to the internet. ( change ethX to you network interface

Hi, I have a wierd problem regarding printing. I use the CUPS-backend on a debian-box to share printers with samba. Sometimes for no apperently reason, a win-box (XP-home) just can't print after a reboot... and no matter how many reboots the win-box makes it just stops working, and dosen't work until samba is restartet.... and its not a samba crash, because other win-boxes prints

Hi, I use Samba and cups on my debian-box to share printers, but sometimes, for no apperently reason, windows machines (XP-pro and XP-home), sudently won't print after reboot and this is only solved by a samba restart. Other times the first print after win-reboot, just gets lost, and never apper in the cups-printing log. It's not domain controled, but everyone is mounting their

Hai Harald, > -----Oorspronkelijk bericht----- > Van: samba [mailto:samba-bounces at lists.samba.org] Namens > Reindl Harald via samba > Verzonden: dinsdag 5 maart 2019 13:18 > Aan: samba at lists.samba.org > Onderwerp: Re: [Samba] getent not working after installing firewall > > > > Am 05.03.19 um 09:18 schrieb L.P.H. van Belle via samba: > > Solution is

I'm writing a pass that looks at the operands of certain non-commutable instructions and swaps a couple of them if certain conditions exist (a register bank conflict in the instruction). If the conflict exists, I build a new instruction which has the 2nd and 3rd operands swapped (using BuildMI). Then I want to get rid of the original instruction. I had done some searching and found that

Hi. I''m newie using LARTC. I have some pc''s and one 512/192kbits conection. I do not want that one PC uses all the bandwidth available. I made this script to limit, but I need that the applications (web browsing, messenger with cam and audo , p2p, etc) in pc''s continue acceding normally Internet. Would work this script? what type of qdisc could be added to htb in

Hi, i'm installing a new mail server for our faculty and want to use the squirrelmail plugin 'avelsieve' (1.9.7). As documented on the dovecot wiki there is a problem in the STARTTLS code and i found a solution (that works for my installation): i've traced the server output in 'get_response' and instead of a script list i saw "IMPLEMENTATION". So i took a look

I start my porting for picoblaze,the soft cpu for fpga ,which is designed by XILINX from MSP430 porting . After some day's work , somethinig looks good , for it can generate for some simple C program: eg : int f1(int a) { return a+1; } but it failed with this : char f() { char a; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++;

Thanks for the information. I still don't know how do I partition registers into different classes from the virtual registers? For instance, I have the function who which iterates over the instructions, but I don't know how to write the function which returns the different register class. void RAOptimal::Gather(MachineFunction &Fn) { // Gather just iterates over the blocks,

This seems a very natural approach but I probably am having a trouble with the iterator invalidation. However, looking at other peephole optimizers passes, I couldn't see how to do this: #define BUILD_INS(opcode, new_reg, i) \ BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) for

Hello, While tuning the MIScheduler for my target, I discovered a code that unnecessarily restricts the scheduler. I think this is a bug, but I would appreciate a second opinion. In file ScheduleDAGInstrs.cpp, the function MIsNeedChainEdge determines whether two MachineInstrs are ordered by a memory dependence. It first runs through the standard criteria (Do both instructions access memory?

I'm trying to understand the Win64 case of the code below, from X86RegisterInfo.cpp: // If this is x86-64 and the Red Zone is not disabled, if we are a leaf // function, and use up to 128 bytes of stack space, don't have a frame // pointer, calls, or dynamic alloca then we do not need to adjust the // stack pointer (we fit in the Red Zone). if (Is64Bit &&

> This sounds like the ADJCALLSTACK DOWN/UP 'instructions' around the call > aren't set right, or you have declared a SP offset. It doesn't look like > the ARM backend does this, so this is probably the problem. The ARM backend currently doesn't use a frame pointer. It uses the same technique of the PPC backend to avoid add/subs around calls. In the PPC backend we

This patch add an emulation for the LSI MegaRAID SAS HBA. It is using SG_IO to forward / pass through SCSI commands to the underlying block driver, so no emulation is done currently. Signed-off-by: Hannes Reinecke <hare at suse.de> --- Makefile.hw | 2 +- hw/megasas.c | 1134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/pci_ids.h | 2 + 3 files changed, 1137

This patch add an emulation for the LSI MegaRAID SAS HBA. It is using SG_IO to forward / pass through SCSI commands to the underlying block driver, so no emulation is done currently. Signed-off-by: Hannes Reinecke <hare at suse.de> --- Makefile.hw | 2 +- hw/megasas.c | 1134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/pci_ids.h | 2 + 3 files changed, 1137

Dear R-Helpers, I'm working with immunoassay data and 5PL logistic model. I wanted to experiment with different forms of weighting and parameter selection, which is not possible in instrument software, so I turned to R. I am using R 2.14.2 under Win7 64bit, and the 'nls' library to fit the model - I started with the same model and weighting type (1/y) as in the instrument to see

Hi llvmdev, I'm trying to figure how llvm remembers stack slots allotted to callee saved registers on x86. In particular, llvm pushes registers in decreasing order of FrameIdxs [1], so the offsets they get (as returned by MFI->getObjectOffset) don't directly correspond to their actual stack locations. In X86FrameLowering's emitCalleeSavedFrameMoves, when emitting DWARF

After running several days in the same configuration, my 3.0.6 nmbd crashed with the above error (see log below). Maybe there is a connection to this message some seconds before: register_name_response: server at IP 192.168.0.4 rejected our name registration of AK<1d> IP 192.168.0.12 with error code 6. The ip .4 machine is a win2k server, which works (or should work) as an ordinary

I'm having trouble with virtual registers/register allocation in my back-end. Basically the FastRegAlloc pass is generating calls to storeToStackSlot and loadFromStackSlot, in which we build new machine instructions, which are then _not_ processed by the reg allocator. I understand that BuildMI is changing the list of MachInst. that the allocator is iterating over, but we need to have a new

On 05/07/2019 20:03, Robert A Wooldridge via samba wrote: > On 07/05/2019 01:55 PM, Rowland penny via samba wrote: >> I currently run tinydns and dnscache on my proxy machine.? I was >> hoping to keep that going.? I have a Windows Server2004 doing DC work >> right now.? Need to update that. >>> >>> -- >>> Bob Wooldridge >>> >> You