similar to: Superimpose two graphs

Hi dear all, the following code is correct. but I want to use non-numeric x-axis, for example if I replace time <- seq(0,72,6) by month <- c("Jan","Feb","Mar","Apr","May","Jun","Jul","Aug","Sep","Oct","Nov","Dec","Pag") Ofcourse I use factor(month) instead of

Oh sorry. An example say lots more than words. The data below, when submitted to twoord.plot return the mentioned error. Rain are bars and Salt lines, the bars appear and the error occurs with the salt data. Point Rain Salt Fev/03 365.6 13 Mar/03 235 18 Abr/03 115.1 18 Mai/03 47.4 18.75 Jun/03 112 15 Jul/03 156.8 17 Ago/03 66.1 15 Set/03 149.8 14 Out/03 167,1 11.5 Nov/03 269.3 17.5 Dez/03 283.7

Hello Dimitris, I was goggling for some help on Sensitivity vs 1-specificity and saw your link. I hope you can be of help to me in one of the issue that I am facing in generating combo chart(bar chart and plot). I am a novice and have some difficulty in getting this logic correct. I am give a dataset (I am attaching a sample dataset). I am using a barplot() and passing values for

Hi, I want to plot two variables on the same graph but with two y axis just like what you can do in Excel. I searched online that seems like you can not achieve that in ggplot. So is there anyway I can do it in a nice way in basic plot? Suppose my data looks like this: Weight Height Date 0.1 0.3 1 0.2 0.4 2 0.3 0.8 3 0.6 1

Hi all, I have scoured the archives of this forum but nothing quite seems to fit the bill... I would like to plot a graph displaying two variables (y axes) that share date as the x axis. However, the date values for each variable are not the same - for example, some parasitoids were not released on days that collections from the trap took place, whilst sometimes releases did occur on the same

You are welcome. I changed the pattern, the same old error pop up again, crash in the same place. Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!

def STOREbos { // InstructionEncoding Instruction RPPInst RPPInstMMEMrr &nbsp; field bits<32&gt; Inst = { 0, 0, 0, 1, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

Hi Krzysztof, Today I try it on llvm9.0.0 version. &nbsp; def bos : RPPInstMMEMrr<OPC_STORE, &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift), &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1,

On Thu, 13 Dec 2018 at 21:41, Friedman, Eli <efriedma at codeaurora.org> wrote: > > On 12/13/2018 6:25 AM, Alex Bradbury wrote: > > There's also likely to be cases where you want to calculate the demanded bits > > in order to determine if e.g. a W-suffixed instruction can be selected for > > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match

Hi Guys, Here is the setup. LVS NAT cluster with director (dir), backup director (bdir), and two realservers (rs1 and rs2) running apache webserver. SSH DSA key-based authentication set up between rs1 and rs2 in order to facilitate automated (via cron) mirorring of htdocs directories. All works fine untill I decide to host DNS on the same cluster. As soon as I start BIND on rs1, ssh no longer

I've been looking to see if there's a way to get the instruction below (SMAC) emitted from a higher-level construct, but I'm starting to think this is unrealistic. To do so, I'd have to tie-in two other instructions: Firstly, clearing the ASR18 and Y register somewhere near the start of the method, then copying out the value of these registers somewhere near the end of the method,

I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made

Hi, I've implemented parallelization in one of my packages using the 'parallel' package -- many thanks for providing it! In my package I'm importing 'parallel' and so added it to the DESCRIPTION file's 'Import:' tag and also added a 'importFrom("parallel", ...)' statement in the NAMESPACE file. Parallelization works nicely, but my package

Hi there, I have a data frame DF of over 600 people's short term trade data in time order. Below is the simplified structure of the data. id invest payout [1] 1 10 -1 [2] 1 33 33 [3] 1 20 -5 [4] 2 200 33 [5] 2 33 -20 [6] 3 5 -5 [7] 3 5

Hi, The full trace stack: Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! [ 85%] Building X86GenEVEX2VEXTables.inc... &nbsp;#0 0x000000000081b9b5

Hello, InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: if (!Hack) PrintFatalError(TheDef->getLoc(), "ERROR: matchable with tied operand '" + Tok + "' can never be matched!");

As previously discussed in an RFC <http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, the RISC-V backend has i64 as the only legal integer type for the RV64 target. Thanks to variable-sized register class support, this means there is no need for duplication of either patterns or instruction definitions for RV32 and RV64. It's worth noting that RV64I is a different base

Hi Daniel, I defined checkEarlyTargetMatchPredicate() to explicitly check for the tied operands, and it worked. I could define an alias like: InstAlias<"oldOP $rd, $rd, $rs1", (NEWOP $rd, $rs1)> However, I had to additionally change AsmMatcherEmitter 'Hack' variable setting to allow the repeated operand $rd in the AsmString. Do you or anyone else know the history

Hi, On Instructions you can use checkEarlyTargetMatchPredicate() to check that the operands are the same. There's an example of that in MipsAsmParser.cpp for DATI and DAHI. I can't think of a reason TableGen couldn't be made to allow this for InstAlias too. > On 15 Dec 2017, at 02:12, via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hello, > > InstAlias

Hi all, I've been trying to figure out how to superimpose a histogram on a biplot that shows the relative contribution of each axis. I have been using the NIPALS function (http://biomserv.univ-lyon1.fr/~dray/ files/softwares/nipals.R) to run principal component analyses. Here is a toy example. source("http://biomserv.univ-lyon1.fr/~dray/files/softwares/nipals.R")