similar to: Identify scripts connecting to the asterisk manager

Hello, I have previously open a topic on the mailing list about deadlocking on Asterisk 1.2.35. After upgrading to 1.4.29.1 we still experienced the same problem : Mar 5 12:05:56] DEBUG[8647] channel.c: Avoiding initial deadlock for channel '0xb7689840' [Mar 5 12:06:41] DEBUG[7130] channel.c: Avoiding deadlock for channel '0xb7c04788' [Mar 5 12:06:41] DEBUG[7130]

We are having an issue with Asterisk 1.6.1 and the MWI turning on when a user doesn't have voicemail. We see random MWI lights come on and the phone indicates a random number of messages (its been anywhere from 1-14) when a server reload is done. I just checked one user, they have no messages old or new and the phone (Polycom IP330) indicates that they have 2 messages. The user will check for

Was my question not understood? Hello, I would like to connect 2 asterisk boxes together, so this is my scenario: Asterisk Main: it is connected to many sip providers and its main purpose as a call termination forwarder. Asterisk B: it?s connected to E1, and its purpose to terminate calls. It will receive SIP messages from Asterisk_Main, but there will be no voice traffic

Hello, I am new to Asterisk and new to this list. I got Asterisk setup and running using Asterisk@home, and purchased a PolyCom SoundPoint IP500 phone to test out. I cannot get the phone to talk to the Asterisk box. On bootup of the phone, it tells me that it cannot contact boot server. Why is that? It gets an IP fine, and I have also tried manually setting the IP of the phone and the Asterisk

Hi, Just to clarify I am looking for a whole machine function analysis not just something restricted to within a machine basic block. Thanks. Regards, Venu. From: Raghavan, Venugopal Sent: Saturday, September 02, 2017 12:56 PM To: llvm-dev at lists.llvm.org Subject: Reaching definitions on Machine IR post register allocation Hi, Given a definition of a register by a machine instruction in

Hi, Thanks for your help! I've checked the sources that you mentioned. Currently, I think that I would need to implement a FunctionToLoopNestPassAdaptor which is essentially the same as the FunctionToLoopPassAdaptor but operates only on LI.getTopLevelLoops(). We might also need a LNPMUpdater (LoopNestPassManagerUpdater) which disallows adding inner-loops back into the pipeline, and

All, Having trouble getting answer from Verizon. I believe Asterisk will let me specify a name and number that is sent to the PSTN (Verizon) of outgoing calls. For instance, if I have a client, First Bank, and their toll free number is 888-555-1234, I could send that name and number. Verizon is telling me that they will forward the number I send them, but the name will be my company's

Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but

Hi Krzysztof, In one of your earlier emails in this thread you mentioned that you had some changes which add extra aliases for subregisters. Did you mean for X86? And is it extra register units that you added or aliases? I tried adding extra register units for X86 through some changes in CodeGenRegisters.cpp in TableGen but I am seeing a runtime error in one of my test cases possibly due to the

Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin > On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > AFAIK, no official doc. > You can probably get better help if you ask specific questions (which part of the code you don't understand). > > On Thu, Jul 6, 2017 at 9:53

Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a

Hi, Sorry I took a long time to reply as it took me some time to get some understanding of the code even to ask some specific questions (I have a test case in which LSR does not kick in and wanted to understand the code to figure out why it was not kicking in). Here are some specific questions I have: 1) It appears that LSR works only for the inner-most loop. Is this correct? Can you tell

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Hi Venu, FWIW, I have a pass that does copy propagation after RA [1] (currently only within a basic block) that should be enabled some time in the not-too-distant future. It has been reviewed and accepted, but I'm currently working on getting a slight change to the MachineOperand representation [2] that should make the copy propagation change much simpler. I believe this change to

Hi, I was interested in trying out LLVM BOLT and generated profile data using Linux perf using the following: perf record -e cycles:u -o perf.data <command> This is without the use of LBR so I understand the performance improvements may not be much but this was more for becoming familiar with BOLT's commands. I then run: perf2bolt -nl -p perf.data -o perf.fdata <binary> and I

Hi Venu, This is happening because there is an implicit def of ECX on the COPY instruction. This was an issue on Hexagon as well. Let me give you some background. There are two kinds of implicit defs (and implicit uses, but I'll refer only to defs for brevity): (1) Those that indicate that some physical register (that is not an operand) is modified by a given instruction (EFLAGS is a good

Hi, My name is Venugopal Raghavan and I work in AMD. I was trying to understand the code in the file LoopStrengthReduce.cpp but I am making very slow progress. Is there any additional documentation available that would help me understand the code, like a PPT presentation or a design document or maybe a paper? I did not find anything on the Internet. There are comments interspersed in the code

uggggh, Friends don't let friends send HTML email. A friendly request that you be considerate to those that do not want email in virii susceptible formats. Myles. <p>Lorenzo banged on his keyboard and his computer puked the following.... <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META content="MSHTML

I talked to Chandler about the name "offload_libs" vs "parallel_libs" and he said he thinks "offload" is too narrow of a term for the scope he sees for this subproject. One example he brought up was AVX 512. He thinks that code explicitly targeting CPU parallelism should also be included in this project, even though it doesn't fit in the category of

I did a more thorough read through liboffload and wrote up a more detailed doc describing how StreamExecutor platforms relate to libomptarget RTL interfaces. The doc also describes why the lack of support for streams in libomptarget makes it impossible to implement some of the most important StreamExecutor platforms in terms of libomptarget (