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We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one of our code generation tests is breaking in 3.9. The test is: ; RUN: llc < %s -march=xstg | FileCheck %s define i64 @bclr64(i64 %a, i64 %b) nounwind readnone { entry: ; CHECK: bclr r1, r0, r1, 64 %sub = sub i64 %b, 1 %shl = shl i64 1, %sub %xor = xor i64 %shl, -1 %and = and i64 %a, %xor ret i64

Dear all, I have noticed a little change in the behaviour of as.factor from R-2.2.1 to R-2.3.0, and can't find it in the NEWS. In R-2.3.0: > times <- 1:5 > class(times) <- "Date" > as.factor(times) [1] 1 2 3 4 5 Levels: 1 2 3 4 5 In R-2.2.1: > as.factor(times) [1] 1970-01-02 1970-01-03 1970-01-04 1970-01-05 1970-01-06 Levels: 1970-01-02 1970-01-03 1970-01-04

Dear all, I have noticed a little change in the behaviour of as.factor from R-2.2.1 to R-2.3.0, and can't find it in the NEWS. In R-2.3.0: > times <- 1:5 > class(times) <- "Date" > as.factor(times) [1] 1 2 3 4 5 Levels: 1 2 3 4 5 In R-2.2.1: > as.factor(times) [1] 1970-01-02 1970-01-03 1970-01-04 1970-01-05 1970-01-06 Levels: 1970-01-02 1970-01-03 1970-01-04

Setting the ISD::ROTL to Expand doesn't work? (via SetOperation) You could also do a Custom hook if that's what you're looking for. On Thu, Nov 3, 2016 at 5:12 PM, Phil Tomson <phil.a.tomson at gmail.com> wrote: > ... or perhaps to rephrase: > > In 3.9 it seems to be doing a smaller combine much sooner, whereas in 3.6 > it deferred that till later in the

Is there any way to get it to delay this optimization where it goes from this: Initial selection DAG: BB#0 'bclr64:entry' SelectionDAG has 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6

I am trying to reproduce some old SAS PROC MIXED code using R and nlme. The data consists of emission readings from vehicles and fuel properties. All variables are real numbers except "study" and "vehicle", which are character. Unfortunately, since the data are confidential, I'm unable to provide an example. The original SAS v6.12 code is provided below:

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

One option may be to prevent the formation of ROTL, if possible, and then generating rol by hand. Marking it as "expand" would likely stop the DAG combiner from creating it. Then you could "preprocess" the selection DAG before the instruction selection and do the pattern matching yourself. -Krzysztof On 11/3/2016 4:24 PM, Phil Tomson via llvm-dev wrote: > I could try

Dear Dennis, Your question assumes that people know both SAS PROC MIXED and R nlme. Only a limited number of people do. Add the mathematical formulation of the model. That will increase the number of people that can help you. Adding the number of levels in each categorical variable and the number of observation per group is useful too. Best regards, ir. Thierry Onkelinx Instituut voor natuur-

I have a data.frame as the following: var1 var2 9G/G09 abd89C/T90 10A/T9 32C/C 90G/G A/A . . . . . . 10T/C 00G/G90 What I want is to get the letters which are on the left and right of '/'. for example, for "9G/G09", I only want "G", "G", and for "abd89C/T90", I only want "C" and

But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I

http://deancollinsblog.blogspot.com/2007/03/microsoft-buys-tellme.html I thought I would email this post I made on my blog from yesterday as a way of stimulating discussion on this. It looks like the Asterisk community is no closer to getting a Pre-Paid 'Offboard Speech Recognition Processing' SIP gateway than ever. I've left the

Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17

Dear all, Please suggest me how can I do it. I have a matrix which look like following: x1 x2 x3 t1 .01 0.3 0 t2 0 0.1 0.01 t3 0 .01 .01 t4 0 0 t5 5 0 0 t6 0 0 0 t7 0 0 0 t8 0 0 0 t9 0.6 0 0 t10 0 0 0.66 t11 0 0.6 0.11 t12 0 0.4 0 I want to sort decreasing order in each column based on rows. and then to display only those rows which has a value. The expected out put matrix will

Hello all. I wish to read a large data set into R. My current issue is in getting the data so that R would be able to access it. Using read.table won't work since the data is over 1GB in size (and I am using windows XP), so my plan was to read the file chunk by chunk and each time move it into bigmemory (I'll play with that when the time will come, maybe ff is better ?!). I encountered

dear list: I need help to achieve a simpler code to complete a task I'm performing. here is an example: dat<-expand.grid(a=seq(1,5),b=seq(1000,1005)) I want to add a new column dat$c in that: t1<-ifelse(dat$a==1&dat$b==1001,1001,0) t2<-ifelse(dat$a==2&dat$b==1002,1001,0) t3<-ifelse(dat$a==3&dat$b==1003,1001,0) t4<-ifelse(dat$a==1&dat$b==1002,1002,0)

Hi List, I have start and end times of events structure(list(start = c("15:00", "15:00", "15:00", "11:00", "14:00", "14:00", "15:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00", "12:00",

Thanks a lot for the suggestions! I will look into using vld1/vst1, sounds good. I am custom lowering the bitcasts, that's now the only place where FP_TO_FP16 and FP16_TO_FP nodes are created to avoid inefficient code generation. I will double check if I can't achieve the same without using these nodes (because I really would like to get completely rid of them). Cheers, Sjoerd.

Hi Bob, This has turned out to be what appears to be a very obscure binutils bug. I'm working on a test case for it now. I have a patch for Mips16 llvm which works around the issue for now. In general, pure risc architectures have no pity for compiler and toolchain developers. Mips16 is way more extreme in this way than mips32. In mips32, there is no PC register or PC relative

> The underlying liveness datastructure is a list of ranges where each vreg is alive > (ranges in terms of instructions numbered). I remember a couple of later linear scan > papers describing the same thing (Traub et.al. being the first if I remember correctly). > That should be as accurate as you can get in terms of liveness information. It depends on the details. For example, given