similar to: Exporting list with unequal length of rows

On Wed, 2016-02-17 at 11:24 +0900, ashutosh srivastava wrote: > > I have compiled R from source in local user account (at non default > > location). R seems to be working fine but issuing plot() command opens a > > window (supposedly graph, but nothing is visible) and then R terminal also > > freezes. Any suggestions? We found an older version of x11 and this worked for

Hi, I am not been able to contact with mentor of this project. Can someone else from the community help me with this ? Regards, Anusha Srivastava On 3 March 2018 at 11:16, Anusha Srivastava <sidd.sinha89 at gmail.com> wrote: > Hi Martin, > > Any update on this ? > Regards, > Anusha Srivastava > > > On 28 February 2018 at 23:37, Anusha Srivastava <sidd.sinha89

Dear R users I have compiled R from source in local user account (at non default location). R seems to be working fine but issuing plot() command opens a window (supposedly graph, but nothing is visible) and then R terminal also freezes. Any suggestions? Following is the session info output. > sessionInfo() R version 3.2.3 (2015-12-10) Platform: x86_64-pc-linux-gnu (64-bit) Running under:

On Fri, May 4, 2012 at 6:50 PM, vaibhav srivastava <vaibhavcse30 at gmail.com>wrote: > > Hi all, > Since I want to run Samba without modifying my existing kernel. Please > tell me what are the requirements for the same. > What are the package list required in kernel before installing samba. > thanks in advance. > -- > Thanks and Regards, > Vaibhav Srivastava >

> On Mar 20, 2015, at 8:02 PM, Nema, Ashutosh <Ashutosh.Nema at amd.com> wrote: > > > Yes, this is what I was proposing above and here ;): > Thanks Adam it’s for confirming J NP :). > > > No, not hasLoopInvariantStore but hasAccessToLoopInvariantAddress. > Its only for invariant stores[not loads], Using ‘hasLoopInvariantStore’ (or a name with invariant store)

So, I won't know the called function statically, Right? -------------------------------------------- Qiuping Yi Institute Of Software Chinese Academy of Sciences On Wed, Jan 20, 2016 at 2:24 PM, Nema, Ashutosh <Ashutosh.Nema at amd.com> wrote: > Typically for C++ virtual function you will see an indirect callSite > (unless not de-virtualized). > > > > Regards, >

> On Mar 19, 2015, at 9:46 PM, Nema, Ashutosh <Ashutosh.Nema at amd.com> wrote: > > Thanks Adam for your reply. > > From: Adam Nemet [mailto:anemet at apple.com <mailto:anemet at apple.com>] > Sent: Friday, March 20, 2015 3:23 AM > To: Nema, Ashutosh > Cc: Hal Finkel; Philip Reames; llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu> > Subject:

On Wed, May 16, 2018 at 1:24 AM, Nema, Ashutosh <Ashutosh.Nema at amd.com> wrote: > Hi Sanjoy, > > Your inputs really helped. > > Using “isImpliedCond”, able to relate and find the min for cases like: > > SCEV1: (-1 + (sext i32 %n.addr.058 to i64))<nsw> > SCEV2: 0 > Extra-Condition: (n.addr.058 > 7) > Result: ‘0’ (SCEV2) > > I have another case

Hi, I would like to participate in GSOC 2018 with Xorg to contribute to project "Initial Nouveau Vulkan driver' I would need some help in how to get started with the same. Regards, Anusha Srivastava

Yes, I can get "SCEVAddRecExpr" from operands of "(sext i32 {2,+,2}<%for.body4> to i64)". So whenever SCEV cast to "SCEVAddRecExpr" fails, we have drill down for such patterns ? Is that the right way ? Regards, Ashutosh -----Original Message----- From: Nick Lewycky [mailto:nicholas at mxc.ca] Sent: Thursday, March 19, 2015 1:02 PM To: Nema, Ashutosh Cc:

Hi Ashutosh, > On Mar 16, 2015, at 9:06 PM, Nema, Ashutosh <Ashutosh.Nema at amd.com> wrote: > > Hi Adam, > > From: Adam Nemet [mailto:anemet at apple.com <mailto:anemet at apple.com>] > Sent: Wednesday, March 11, 2015 10:48 AM > To: Nema, Ashutosh > Cc: llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu> > Subject: Re: [LLVMdev] RFC: Loop

Yes, masked load/store/gather/scatter are completed. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 01:20 To: Demikhovsky, Elena <elena.demikhovsky at intel.com> Cc: Sanjay Patel <spatel at rotateright.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to

No. Gather operation is slow on AVX2 processors. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 20:48 To: Sanjay Patel <spatel at rotateright.com> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to force

<Copied Cong> Thanks Elena. Mostly I was interested in why such a high cost 30 kept for TRUNCATE v16i32 to v16i8 in SSE41. Looking at the code it appears like TRUNCATE v16i32 to v16i8 in SSE41 is very expensive vs SSE2. I feel this number should be same/close to the cost mentioned for same operation in SSE2ConversionTbl. Below patch from Cong Hou reduce cost for same operation in SSE2

Hi Sanjoy, Your inputs really helped. Using “isImpliedCond”, able to relate and find the min for cases like: SCEV1: (-1 + (sext i32 %n.addr.058 to i64))<nsw> SCEV2: 0 Extra-Condition: (n.addr.058 > 7) Result: ‘0’ (SCEV2) I have another case where trying to find min between two SCEVs under an extra condition. “isImpliedCond” is not helping for below case, may be I’m missing something:

That makes great sense. It would be great if we have profitability mode to see the necessity to use gathers. Or it also would be good if there is a compiler option for the users to enable LLVM to generate the gather instructions no matter it is faster or slow. Best, Zhi On Fri, Feb 26, 2016 at 12:49 PM, Sanjay Patel <spatel at rotateright.com> wrote: > If I'm understanding

Sorry typo in test case, Please ignore previous mail. Consider below case: for (j=1; j < itr; j++) { - - - - for (i=1; i < itr; i++) { { temp= var[i << 1]; - - - - - } } In the above example, we are unable to get "SCEVAddRecExpr" for "var[i << 1]" Its "SCEVAddRecExpr" is computable in *Outer Loop* I

On 03/14/2017 11:21 AM, Adam Nemet wrote: > >> On Mar 14, 2017, at 6:00 AM, Nema, Ashutosh <Ashutosh.Nema at amd.com >> <mailto:Ashutosh.Nema at amd.com>> wrote: >> >> Summarizing the discussion on the implementation approaches. >> Discussed about two approaches, first running ‘InnerLoopVectorizer’ >> again on the epilog loop immediately after

If I'm understanding correctly, you're saying that vgather* is slow on all of Excavator, Haswell, Broadwell, and Skylake (client). Therefore, we will not generate it for any of those machines. Even if that's true, we should not define "gatherIsSlow()" as "hasAVX2() && !hasAVX512()". It could break for some hypothetical future processor that manages to

On 03/14/2017 11:58 AM, Michael Kuperstein wrote: > I'm still not sure about this, for a few reasons: > > 1) I'd like to try to treat epilogue loops the same way regardless of > whether the main loop was vectorized by hand or automatically. So if > someone hand-wrote an avx-512 16-wide loop, with alias checks, and we > decide it's profitable to vectorize the