similar to: creating functions question

Hi all, Our target does not have native support for 64-bit integers, so we rely on library calls for certain operations (like sdiv). We recently ran into a problem where these operations that are expanded to library calls aren't maintaining the proper ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2:

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,

Hi All, I am observing something i suspect is a misbehaviour of the register allocator which impacts the performance of patchpoints. This occurs in the context of an abstract machine which in some places uses inline caches. The problematic code looks like this: entry: ; Initialize the abstract machine %db = call create_big_seldom_used_database() ; do a lot of things which increases register

On Wed, 21 Oct 2009, Lang Hames wrote: > There are any number of things that can go wrong in register allocation, so > it's hard for me to guess without seeing your code. > > Possible issues: > > 2) How are you making sure that interfering virtregs never receive the same > physreg? If you're using the LiveIntervals analysis (and the >

Hi all, I have TDM2406E with 24FXO ports connecting to 10 POTS line sitting in my office. the out going calls symptom like when called party pickup the phone but the calling party still hearing the ring tone from the IP phone. Please light me up. it been many sleepless night by googling around trying to get the right answers. The digium card running on Intel 915G chipset. Below are my zaptel

Hi Susan, > 1. I tried running the PBQP allocator (as a dynamic pass), but that didn't > work.... Can you tell from this what I'm doing wrong? > The PBQP allocator is built into the LLVM CodeGen library, so the "-regalloc=pbqp" option is already available in llc. If you've built a copy of the PBQP allocator in a separate library it will try to re-register

We have a test that looks like this… define void @array16_store() { ; CHECK-LABEL: array16_store: ; CHECK: ldi [[REG1:r[0-9]+]], 204 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; CHECK: sts int.array+3, [[REG2]] ; CHECK: sts int.array+2, [[REG1]] ; CHECK: ldi [[REG1:r[0-9]+]], 187 ; CHECK: ldi [[REG2:r[0-9]+]], 170 ; CHECK: sts int.array+1, [[REG2]] ; CHECK: sts int.array, [[REG1]] ; CHECK: ldi

Hi all, In several of our tests, I have noticed that the register allocator allocates to virtual registers in a different order when compiling with the clang option -g. Before entering the register allocator, the code is identical when compiling with and without -g (with the exception of " DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index

Hi list, in our LLVM-based-project we are writing a backend for our processor. The architecture is a quite straight-forward RISC, but it does not have hardware interlocks, i.e. data hazards involving memory access must be resolved by the compiler, either by scheduling unrelated instructions or by inserting NOOPs into the load delay slots: ---- For example, code which looks like that: load

I’m not sure if it’s truly deterministic. It always gives the same results (so far) on my machine but I’m not sure that’s enough. My guess is it’s probably going to be deterministic on one machine but might well not be deterministic across environments. Like it might give varying results if cross compiled on different hosts, macOS vs intel Linux vs arm vs s390. (Obviously AVR is always a cross

On Jan 19, 2009, at 9:17 AM, Patrick Boettcher wrote: > Hi list, > > in our LLVM-based-project we are writing a backend for our > processor. The > architecture is a quite straight-forward RISC, but it does not have > hardware interlocks, i.e. data hazards involving memory access must be > resolved by the compiler, either by scheduling unrelated > instructions or >

> On Feb 2, 2017, at 8:20 AM, David Blaikie <dblaikie at gmail.com> wrote: > > The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure. > > The fixes aren't usually too invasive (usually involve something counting instructions where it needs to skip

> On Feb 2, 2017, at 8:20 AM, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure. > > The fixes aren't usually too invasive (usually involve something counting instructions where

Hello, I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register. Example of an addition: load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1 load b, reg1; // -> copies old value of reg1 in reg2 and loads

Each of the data sets contains monthly observations on price indices for 7 countries. I use the fitted values from reg1 in the reg2 model. The interior loop executes without error as long as I explicitly specify the data set, i.e. data=dat70. However the code fails to execute if I specify the model in the form of the commented line, i. e reg1 <-dynlm(form1,data=Dnames[j]) I get the following

To generate code for a target which doesn't have immediate constant as instruction operand, do I (the target specific back-end, XXXTarget) need to provide code to break up the SDNode with constant (like ISD::ADD $reg1, #1) to 2 SDNodes (ISD::LOAD $reg2, #1; ISD::ADD $reg1, $reg2) in my XXXTargetLowering::LowerOperation, or LLVM target-independent framework can do such transformation

Dear R Users, I am looking for an alternative to AIC or BIC to choose model parameters. This is somewhat of a general statistics question, but I ask it in this forum as I am looking for a R solution. Suppose I have one dependent variable, y, and two independent variables, x1 an x2. I can perform three regressions: reg1: y~x1 reg2: y~x2 reg3: y~x1+x2 The AIC of reg1 is 2000, reg2 is

Hi folks, Warning: I don't know if the result I am getting makes sense, so this may be a statistics question. The fitted values from my binomial lmer mixed model seem to consistently overestimate the cell means, and I don't know why. I assume I am doing something stupid. Below I include code, and a binary image of the data is available at this link:

I have a puzzle.... When I include an interaction in the model, many predicted probabilities are above 1. Is that a problem with my model? I thought the predicted prob can't be bigger than 1... Any help would be really appreciated! Thanks! K. reg1<-glm(pyea~male+edu+married+inc+relig+factor(time)+ factor(time)*male, data=mydata, family=binomial(link="logit"))

Hi, I am trying to create a scatterplot, coding each point to one of 5 populations. I was successful when I did this for one set of data, yet when I try plotting other data a blank plot appears (although the axes are labelled and I can fit the regression lines from each population). I have tried a variety of things to fix this but nothing seems to work. I can plot the points if I do not