Displaying 6 results from an estimated 6 matches for "zyfwong".
2015 Aug 04
2
[LLVMdev] Help needed about code & data mixing when emit object files
Hi,
I'm building a new backend which can only load very limited range of imm.
So I decided to use constant pool, and place constant pool entries close
enough to instructions use the entries (we have very limited range
PC-relative memory load). However, lld & llc output the object files that
gather all constant pool entries into one section. How can I make them mix
these entries into code
2016 Jul 25
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
...this kind of attribute is not limited to IPRA so we
> have initiated discussion on mailing list
> https://groups.google.com/d/topic/llvm-dev/w70_WljNCHE/discussion.
>
> I have also implemented a patch which fixes a very subtle bug in regmask
> calculation. Thanks to zan jyu Wong <zyfwong at gmail.com> for bringing this
> to notice.
>
> For example if CL is only clobbered than CH should not be marked clobbered
> but CX, RCX and ECX should be mark clobbered. Previously for each modified
> register all of its aliases are marked clobbered by markRegClobbred() in
>...
2015 Oct 05
2
handling "overlapping" register classes
I'm working on generating code for a machine that has a register set kind
of like the 68000.
For those who don't recall, the 68K has 8 Data registers that can be used
for ordinary integer
instructions like add, subtract, multiply, shift, etc., and 8 Address
registers that can be use for
integer addition and a few other things, especially base registers for
addressing modes.
The Data
2016 Jul 10
2
[GSoC 2016] [Weekly Status] Interprocedural Register Allocation
Hello LLVM Developers,
Please feel free to send any ideas that you can think to improve current
IPRA. I will work on it and if possible I will implement that.
Please consider summary of work done during this week.
Implementation:
============
The reviews requests has been updated to reflect the reviews.
Testing:
=====
To get more benefit from IPRA I experimented it with LTO and results
2016 Jul 13
6
IPRA, interprocedural register allocation, question
Vivek,
I apologize if you took my original email as a request for implementation,
I meant to be asking what is already available, I think the answer to that
is the ‘preserves_most’ and ‘preserves_all’ attributes, but I will also
Use ‘regmask’ if those prove to be too sub-optimal.
I am still interested in figuring out the necessary and sufficient conditions
For LLC to do optimal IPRA
2015 May 21
2
[LLVMdev] How can I remove these redundant copy between registers?
Hi,
I've been working on a Blackfin backend (llvm-3.6.0) based on the previous
one that was removed in llvm-3.1.
llc generates codes like this:
29 p1 = r2;
30 r5 = [p1];
31 p1 = r2;
32 r6 = [p1 + 4];
33 r5 = r6 + r5;
34 r6 = [p0 + -4];
35 r5 *= r6;
36 p1 = r2;
37 r6 = [p1 + 8];
38 p1 = r2;
p1 and r2 are in different register classes.
A p*