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...ou mean this? > ** > > ** > *tanks, > * > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -- Yours truly, Zhang Zuyu(张祖羽) ----------------------------------------------------------- College of Computer Science and Technology, Harbin Engineering University -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111202/1c3c9dc3/atta...

Hi , I want to create a bc file by llvm-gcc, and need to pass a input file when create this file, how can i do it?I saw options in "llvm-gcc [options] filename" but it could not help me. I have an another problem too. my program contains some C file , that main function use those, but i don't know how create bc file with regard to other file.  tanks, -------------- next part

...r this is a real bug. > > Thank you, > Alex > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -- Yours truly, Zhang Zuyu(张祖羽) ----------------------------------------------------------- College of Computer Science and Technology, Harbin Engineering University -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110907/5043aa49/atta...

Hi everyone, I found some peculiar behavior of TableGen when generating [TARGET]GenRegisterInfo.inc. Some register overlaps are generated twice in this file, leading to a compilation error. I think this is because in RegisterInfoEmitter.cpp, RegisterAliases are declared as "std::map<Record*, std::set<Record*>, LessRecord>" and a requirement for std::map is that the

...ascending memory locations. Register X is not affected or updated. If register X is part of the quadrant being transferred, the value stored for this register is undefined. Condition Code: Instruction Fields: same to LDQ -- Yours truly, Zhang Zuyu(张祖羽) ----------------------------------------------------------- College of Computer Science and Technology, Harbin Engineering University -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110623/6fc7245f/atta...

...he attachment is my resume. Everyone here can call me Tony. And I will try my best to do it. btw, later I will go to Tsinghua University to do some similar work like basicblockprofiling, of course based on llvm. Blow is the project information: http://formes.asia/cms/ -- Best Regards, Zhang Zuyu(张祖羽) ----------------------------------------------------------- College of Computer Science and Technology, Harbin Engineering University Email: hitzzy at gmail.com QQ: 339753431 Gtalk: hitzzy at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://...

Hello > Finally, I don't know how to describe following instructions in > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files > should I use to finish this description? Do you need the isel support for them? If yes, then you should custom isel them. iirc ARM and SystemZ backends have similar instructions, while only the first one supports full isel for them. In

...me entry points for several PHI instructions in one basic block, such as %for.inc14 and %entry. 2) the same step but may in two different directions, such as %indvars.iv and %i.020 are both changed by 1, although the former increase and the latter decrease. Any suggestions are welcome! Regards, Zuyu Zhang -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120731/a93ad7ee/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: bubbleSort.c Type: text/x-csrc Siz...