search for: zmm5

Hi, It seems LLVM-MC is broken with Avx512? $ echo "vinserti32x4 \$1, %xmm21, %zmm5, %zmm17"|./Release+Asserts/bin/llvm-mc -assemble -arch=x86-64 -show-encoding -x86-asm-syntax=att .text vinserti32x4 $1, %xmm21, %zmm5, %zmm17 # encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01] $ echo "0x62,0xa3,0x55,0x48,0x38,0xcd,0x01" |./Release+Asserts/bin/llvm-mc -disas...

...instructions as well as the assembler. I looked but didn’t see any disassembler tests for avx512. -Jim On Dec 12, 2013, at 7:32 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > Hi, > > It seems LLVM-MC is broken with Avx512? > > > $ echo "vinserti32x4 \$1, %xmm21, %zmm5, %zmm17"|./Release+Asserts/bin/llvm-mc -assemble -arch=x86-64 -show-encoding -x86-asm-syntax=att > .text > vinserti32x4 $1, %xmm21, %zmm5, %zmm17 # encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01] > > $ echo "0x62,0xa3,0x55,0x48,0x38,0xcd,0x01" |./Release+Assert...

...# zmm23 = >>>>> [0,1,2,3,4,5,6,7] >>>>> vpbroadcastq zmm2, qword ptr [rip + .LCPI0_2] >>>>> vpbroadcastq zmm3, rsi >>>>> add rsi, 3856000 >>>>> vpbroadcastq zmm4, qword ptr [rip + .LCPI0_3] >>>>> vpbroadcastq zmm5, qword ptr [rip + .LCPI0_4] >>>>> vpbroadcastq zmm6, qword ptr [rip + .LCPI0_5] >>>>> kxnorw k1, k0, k0 >>>>> kshiftrw k1, k1, 8 >>>>> vpbroadcastq zmm7, qword ptr [rip + .LCPI0_6] >>>>> .p2align 4, 0x90 >>>>>...

...alling convention while adding support for HVA and vector types. There are four main differences: - Floating-point types are considered vector types just like __m128, __m256 and __m512. The first 6 vector typed arguments are saved in physical registers XMM0/YMM0/ZMM0 until XMM5/YMM5/ZMM5. - After vector types and integer types are allocated, HVA types are allocated, in ascending order, to unused vector registers XMM0/YMM0/ZMM0 to XMM5/YMM5/ZMM5. - Just like in the default x65 CC, Shadow space is allocated for vector/HVA types. The size is fixed to 8 bytes per...