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...VM? --Vikram http://www.cs.uiuc.edu/~vadve http://llvm.cs.uiuc.edu/ On Jul 31, 2006, at 1:10 PM, Devang Patel wrote: > llvmgcc4 emits LLVM byte code before executing GCC optimizations, > so one can say that llvmgcc4 disables all GCC optimizations. > > On Jul 31, 2006, at 11:01 AM, Zhiru Zhang wrote: > >> Hi, >> I am trying to turn on the new GCC auto-vectorization feature >> within llvmgcc4. Below is the command I used, but nothing was >> vectorized. Does it mean that llvmgcc4 has disabled this >> optimization and all I can do is to embed SSE...

llvmgcc4 emits LLVM byte code before executing GCC optimizations, so one can say that llvmgcc4 disables all GCC optimizations. On Jul 31, 2006, at 11:01 AM, Zhiru Zhang wrote: > Hi, > I am trying to turn on the new GCC auto-vectorization feature > within llvmgcc4. Below is the command I used, but nothing was > vectorized. Does it mean that llvmgcc4 has disabled this > optimization and all I can do is to embed SSE intrinsics in the &gt...

On Apr 25, 2007, at 4:53 PM, Zhiru Zhang wrote: > Hi Devang, > > You recently mentioned that the pass manager now allows a ModulePass > to require a FunctionPass. I just tried it but ran into errors. Could > you please take a look to see if I did anything wrong? Thanks! I can reproduce this crash. Please file bugzil...

Hi, I am trying to turn on the new GCC auto-vectorization feature within llvmgcc4. Below is the command I used, but nothing was vectorized. Does it mean that llvmgcc4 has disabled this optimization and all I can do is to embed SSE intrinsics in the source code by hand? Thanks! ./llvm-gcc4-x86/bin/llvm-gcc -c -O2 -ftree-vectorize -msse -ftree-vectorizer-verbose=5 -emit-llvm vec.c -o vec.bc

...assManager::runOnFunction(llvm::Function&)+0xff)[0x85ce667] opt(llvm::MPPassManager::getOnTheFlyPass(llvm::Pass*, llvm::PassInfo const*, llvm::Function&)+0x62)[0x85ce85e] opt(llvm::AnalysisResolver::findImplPass(llvm::Pass*, llvm::PassInfo const*, llvm::Function&)+0x33)[0x85cbc39] /home/zhiruz/AutoESL/AutoPilot/trunk/build/obj-Linux-x86-g++/Debug/lib/libLLVMHello.so(llvm::LoopInfo& llvm::Pass::getAnalysisID<llvm::LoopInfo>(llvm::PassInfo const*, llvm::Function&)+0x99)[0x12efc7] /home/zhiruz/AutoESL/AutoPilot/trunk/build/obj-Linux-x86-g++/Debug/lib/libLLVMHello.so(llvm::Loo...

...vadve > http://llvm.cs.uiuc.edu/ > > > On Jul 31, 2006, at 1:10 PM, Devang Patel wrote: > >> llvmgcc4 emits LLVM byte code before executing GCC optimizations, >> so one can say that llvmgcc4 disables all GCC optimizations. >> >> On Jul 31, 2006, at 11:01 AM, Zhiru Zhang wrote: >> >>> Hi, >>> I am trying to turn on the new GCC auto-vectorization feature >>> within llvmgcc4. Below is the command I used, but nothing was >>> vectorized. Does it mean that llvmgcc4 has disabled this >>> optimization and all...

...c. Besides the in-memory exchange of the information, we also want on-disk exchange. That introduces the write-out/parse-in problem. Thanks ----- Original Message ----- From: "Misha Brukman" <brukman at uiuc.edu> To: "Yiping Fan" <fanyp at CS.UCLA.EDU>; "'Zhiru Zhang'" <zhiruz at CS.UCLA.EDU>; "Guoling Han" <leohgl at CS.UCLA.EDU> Cc: <llvmdev at cs.uiuc.edu> Sent: Wednesday, October 20, 2004 11:43 AM Subject: Re: LLVM Compiler Infrastructure Tutorial > I'm CC'ing the llvm-dev list because other people ar...

I'm CC'ing the llvm-dev list because other people are more knowledgeable about the bytecode format/encoding than I am. Please follow-up the replies to the list. On Wed, Oct 20, 2004 at 11:27:53AM -0700, Yiping Fan wrote: > We also want to extend the llvm instructions/intrinsic > functions/types/passes to support our high-level synthesis for > hardware. First of all, we want to

...thesis. Of cource, it is not as powerful as LLVM, and we also want to use many of your transformation/analysis passes. That is why we want to move our project on top of your IR. Thanks, -Yiping ----- Original Message ----- From: Vikram Adve To: LLVM Developers Mailing List Cc: 'Zhiru Zhang' ; Guoling Han ; Yiping Fan Sent: Wednesday, October 20, 2004 3:08 PM Subject: Re: [LLVMdev] Re: LLVM Compiler Infrastructure Tutorial Yiping, Could you describe in a little more detail what your goals are? I agree with Reid and Misha that modifying the instruction definition...

...g Fan <fanyp at cs.ucla.edu> ----- Date: Mon, 31 Oct 2005 17:20:24 -0800 From: "Yiping Fan" <fanyp at cs.ucla.edu> To: "Misha Brukman" <brukman at uiuc.edu>, "guoling han" <leohgl at cs.ucla.edu>, <cong at cs.ucla.edu>, "'Zhiru Zhang'" <zhiruz at cs.ucla.edu> Cc: "Brian Gaeke" <gaeke at uiuc.edu> Subject: Re: LLVM Compiler Infrastructure Hi Misha, How are you doing recently? It has been long time since the last email we exchanged. We used your LLVM compiler in our xPilot behavioral syn...

...it. -Chris >> On Jul 31, 2006, at 1:10 PM, Devang Patel wrote: >> >> > llvmgcc4 emits LLVM byte code before executing GCC optimizations, so one >> > can say that llvmgcc4 disables all GCC optimizations. >> > >> > On Jul 31, 2006, at 11:01 AM, Zhiru Zhang wrote: >> > >> > > Hi, >> > > I am trying to turn on the new GCC auto-vectorization feature within >> > > llvmgcc4. Below is the command I used, but nothing was vectorized. >> > > Does it mean that llvmgcc4 has disabled this opti...

...our > project on top of your IR. Understood! >   >   > Thanks, >   > -Yiping >   Good luck, --Vikram http://www.cs.uiuc.edu/~vadve http://llvm.cs.uiuc.edu/ > > ----- Original Message ----- > From: Vikram Adve > To: LLVM Developers Mailing List > Cc: 'Zhiru Zhang' ; Guoling Han ; Yiping Fan > Sent: Wednesday, October 20, 2004 3:08 PM > Subject: Re: [LLVMdev] Re: LLVM Compiler Infrastructure Tutorial > > Yiping, > > Could you describe in a little more detail what your goals are? I > agree with Reid and Misha that modifying the...

Yiping, Could you describe in a little more detail what your goals are? I agree with Reid and Misha that modifying the instruction definition is usually not advisable but to suggest alternatives, we would need to know more. Also, for some projects it could make sense to change the instruction set. --Vikram http://www.cs.uiuc.edu/~vadve http://llvm.cs.uiuc.edu/ On Oct 20, 2004, at 2:41 PM,

On Wed, Oct 20, 2004 at 11:59:45AM -0700, Yiping Fan wrote: > Yeah. We need to have more extra fields in the instruction. Fo > example, during high-level synthesis, we must schedule an instruction > to a certain control step (or cycle), and bind it to be execute on a > certain functional unit, etc. Since we're talking about "execution" and "scheduling", you