Displaying 2 results from an estimated 2 matches for "zext_i8_to_i16_simpl".
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zext_i8_to_i16_simple
2013 Jan 11
2
[LLVMdev] Sub-Register Allocation
...e could point
me in the right direction of explaining.
The architecture is 68000, which has 8, 16, and 32 bit views of all of it's
data registers. In order to zero extend you can load a big view with zero,
and then copy into the small view.
I'm working on this llvm function,
define i16 @zext_i8_to_i16_simple(i8 %x) {
%1 = zext i8 %x to i16
ret i16 %1
}
I have a pattern where I load the 16 bit portion of the register with 0,
and then copy in the 8 bit portion.
def : Pat<(i16 (zextloadi8 addr:$src)),
(INSERT_SUBREG (MOV16id 0), (MOV8md addr:$src), sub_byte)>;
which produces workin...
2013 Jan 12
0
[LLVMdev] Sub-Register Allocation
...ve a pattern where I load the 16 bit portion of the register with 0, and then copy in the 8 bit portion.
>
> def : Pat<(i16 (zextloadi8 addr:$src)),
> (INSERT_SUBREG (MOV16id 0), (MOV8md addr:$src), sub_byte)>;
>
> which produces working but odd assembly,
>
> zext_i8_to_i16_simple PROC ; @zext_i8_to_i16_simple
> ; BB#0:
> move.b 4(a7), d1
> move.w #0, d0
> move.b d1, d0
> rts
>
> Notice the extraneous use of d1, as
>
> move.w #0, d0
> move.b 4(a7), d0
>
> would work just as well.
LLVM...