search for: zeroornegativeonebooleancont

...are you sure there isn't anything in your target still > expecting an i1? I have specified that Hexagon has an i8 predicate register that represents the true predicate as -1 with a sign extend like this: addRegisterClass(MVT::i8, &Hexagon::PredRegsRegClass); setBooleanContents(ZeroOrNegativeOneBooleanContent); and I'm calling this code just before computeRegisterProperties, that builds the TransformToType table specifying the type promotions: i1 -> i8 i8 -> i8 (legal) i16 -> i32 i32 -> i32 (legal) This would be fine if the register for i8 could be used for any integer operation...

...thing in your target still >> expecting an i1? > > I have specified that Hexagon has an i8 predicate register that > represents the true predicate as -1 with a sign extend like this: > > addRegisterClass(MVT::i8,&Hexagon::PredRegsRegClass); > setBooleanContents(ZeroOrNegativeOneBooleanContent); > > and I'm calling this code just before computeRegisterProperties, that > builds the TransformToType table specifying the type promotions: > > i1 -> i8 > i8 -> i8 (legal) > i16 -> i32 > i32 -> i32 (legal) > > This would be fine if the regis...

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > however, is that they are 8 bits.  The reason for this is

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

...ring(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) { - - const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>(); - + Subtarget = &TM.getSubtarget<AArch64Subtarget>(); // SIMD compares set the entire lane's bits to 1 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); @@ -2050,6 +2050,90 @@ AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op, } } +SDValue +AArch64TargetLowering::LowerGlobalAddressDarwin(SDValue Op, + SelectionDAG &DAG) const { + + EVT PtrVT = getPointerTy(); + SDLoc dl(Op)...