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...at whether you're getting an Instruction* or Constant* and >> everything will be fine. >> >> Nick >> >> >> Best, >> Zhi >> >> >> >> >> >> On Thu, Apr 16, 2015 at 11:55 PM, zhi chen <zchenhn at gmail.com >> <mailto:zchenhn at gmail.com> >> <mailto:zchenhn at gmail.com <mailto:zchenhn at gmail.com>>> wrote: >> >> Yes. I was using this. It seems the produced instruction is >> not >> correct...

...build the function top down and don't look > at whether you're getting an Instruction* or Constant* and everything will > be fine. > > Nick > > >> Best, >> Zhi >> >> >> >> >> >> On Thu, Apr 16, 2015 at 11:55 PM, zhi chen <zchenhn at gmail.com >> <mailto:zchenhn at gmail.com>> wrote: >> >> Yes. I was using this. It seems the produced instruction is not >> correct. There are probably some other problems. I need to recheck >> it. Thanks for your help, Daniel. >> >>...

...'ll get: dupInst <2 x double> <double fadd (double undef, double undef), double fadd (double undef, double undef)> It seems that if simply fails to generate the vectorized FADD instruction. Anything wrong with my code? Best, Zhi On Thu, Apr 16, 2015 at 11:55 PM, zhi chen <zchenhn at gmail.com> wrote: > Yes. I was using this. It seems the produced instruction is not correct. > There are probably some other problems. I need to recheck it. Thanks for > your help, Daniel. > > Best, > Zhi > > On Thu, Apr 16, 2015 at 11:40 PM, Daniel Berlin <dberlin...

...ge CPU. On Fri, Apr 10, 2015 at 6:48 PM, Bruce Hoult <bruce at hoult.org> wrote: > I suppose that depends on your CPU. Do you even have a CPU that supports > operations on <N x i1> as packed bits in vector registers? > > > On Sat, Apr 11, 2015 at 12:43 PM, zhi chen <zchenhn at gmail.com> wrote: > >> Yes, but my point is that there would be some overhead to do cast the <N >> x i1> vectortype to an integerNty. Is there any good way to check not all >> of these N bits in the vectortype are 0s? >> >> On Fri, Apr 10, 2015 at 5:37 P...

...ote: > Sure, if you actually just want an i1 saying whether or not at least one > bit is set to 1, then comparing against 0 is the right thing. > > That should end up generating a unary TST instruction on ISAs that have > one. > > On Sat, Apr 11, 2015 at 12:29 PM, zhi chen <zchenhn at gmail.com> wrote: > >> Thanks, Bruce. So, what is the easiest way to check if there is any bit >> set to 1 in a <N x i1> vector type? I used bitcast instruction to cast it >> into "iN" first and them compare iN to 0. Do you have a better way to do >>...

Value * is the instruction. use dyn_cast<Instruction> to get to it. On Thu, Apr 16, 2015 at 11:39 PM zhi chen <zchenhn at gmail.com> wrote: > But IRBuilder.CreateXYZ only returns a "VALUE" type. Can I get the > instruction created by it? For example, > > IRBuilder<> builder(&*pinst); > Value *val = builder.CreateFAdd(LV, RV, ""); > > How can I get the fadd inst...

Does the insert point also mean inserting before the instruction? On Tue, Apr 21, 2015 at 3:36 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > IRBuilder takes an insertion point. > Use it? > > > On Tue, Apr 21, 2015 at 3:17 PM, zhi chen <zchenhn at gmail.com> wrote: > > The current instruction is: > > > > Instruction *pInst; > > > > How can I create a new instruction, say add, after pInst? > > > > Thanks, > > Zhi > > > > > > > > _____________________________________...

...he architectural features with that implementation detail. On Fri, Feb 26, 2016 at 12:23 PM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > No. Gather operation is slow on AVX2 processors. > > > > - * Elena* > > > > *From:* zhi chen [mailto:zchenhn at gmail.com] > *Sent:* Thursday, February 25, 2016 20:48 > *To:* Sanjay Patel <spatel at rotateright.com> > *Cc:* Demikhovsky, Elena <elena.demikhovsky at intel.com>; Nema, Ashutosh < > Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> > > *...

...ail. > > On Fri, Feb 26, 2016 at 12:23 PM, Demikhovsky, Elena < > elena.demikhovsky at intel.com> wrote: > >> No. Gather operation is slow on AVX2 processors. >> >> >> >> - * Elena* >> >> >> >> *From:* zhi chen [mailto:zchenhn at gmail.com] >> *Sent:* Thursday, February 25, 2016 20:48 >> *To:* Sanjay Patel <spatel at rotateright.com> >> *Cc:* Demikhovsky, Elena <elena.demikhovsky at intel.com>; Nema, Ashutosh < >> Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org...

...> > On Wed, Feb 24, 2016 at 11:39 PM, Demikhovsky, Elena < > elena.demikhovsky at intel.com> wrote: > >> Yes, masked load/store/gather/scatter are completed. >> >> >> >> - * Elena* >> >> >> >> *From:* zhi chen [mailto:zchenhn at gmail.com] >> *Sent:* Thursday, February 25, 2016 01:20 >> *To:* Demikhovsky, Elena <elena.demikhovsky at intel.com> >> *Cc:* Sanjay Patel <spatel at rotateright.com>; Nema, Ashutosh < >> Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org...

No. Gather operation is slow on AVX2 processors. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 20:48 To: Sanjay Patel <spatel at rotateright.com> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to force l...

...ast `pinst` to a pointer to Vector of double, since it (I hope for your sake) is a pointer to integer. What you are trying to do is bitcast a pointer into a vector, which probably will lead to an assert or "bad code that doesn't work". -- Mats On 15 April 2015 at 21:57, zhi chen <zchenhn at gmail.com> wrote: > What I want to do is to change the pInst from : 2%= load double* %1, align 8 > to 2% = load < 2 x double>* %1, align 16, where <2 x double> should be two > double identical double values that is same as the one in the previous > instruction > &gt...

Got it. Thanks. I will try it with the trunk version. On Wed, Jan 20, 2016 at 1:36 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Zhi, > On 20 January 2016 at 13:33, zhi chen <zchenhn at gmail.com> wrote: > > Thanks for your response. The attached is the .bc file after my pass. I > > could generate the assembly with -mcpu=skx but not with -mcpu=core-avx2. > > Could you please take a look? BTW, I am using LLVM-3.7. > > It seems to compile fine on trunk,...

...t; wrote: > LLVM doesn't have a "logical neg" (or "not") operator. That's a C thing. > Do a compare against 0 to create an i1 result, then zero extend the i1 to > the size of integer result you want. > > > On Sat, Apr 11, 2015 at 12:07 PM, zhi chen <zchenhn at gmail.com> wrote: > >> How can I generate LLVM IR for both logical NEG (!)? For example, if I >> have Int32Ty a, >> >> For the bitwise NEG(~): >> >> c = ~a ; >> >> I can use the following API from LLVM: >> >> BinaryOperator *neg =...

Yes, masked load/store/gather/scatter are completed. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 01:20 To: Demikhovsky, Elena <elena.demikhovsky at intel.com> Cc: Sanjay Patel <spatel at rotateright.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to force l...

Say if we have 8 cores, I want to get which core is running the current program. Thanks. On Thu, Nov 19, 2015 at 3:37 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- > > From: "zhi chen" <zchenhn at gmail.com> > > To: "Hal Finkel" <hfinkel at anl.gov> > > Cc: llvm-dev at lists.llvm.org > > Sent: Thursday, November 19, 2015 3:48:02 PM > > Subject: Re: [llvm-dev] Get timestamp and processor ID in the IR > > > > > > Hi Hal, > >...

...> > - * Elena* > > > > *From:* Sanjay Patel [mailto:spatel at rotateright.com] > *Sent:* Saturday, January 23, 2016 18:42 > *To:* Nema, Ashutosh <Ashutosh.Nema at amd.com> > *Cc:* Demikhovsky, Elena <elena.demikhovsky at intel.com>; zhi chen < > zchenhn at gmail.com>; llvm-dev <llvm-dev at lists.llvm.org> > *Subject:* Re: [llvm-dev] how to force llvm generate gather intrinsic > > > > > > On Sat, Jan 23, 2016 at 6:45 AM, Nema, Ashutosh <Ashutosh.Nema at amd.com> > wrote: > > Thanks Sanjay for highlightin...

...> Sounds like a bug, as far as I can tell, -mno-sse should disable all use > of SSE instructions (and thus all uses of xmm registers). Exactly what > version of LLVM, and what instructions from what LLVM IR or C source? > > -- > Mats > > On 14 May 2015 at 18:12, zhi chen <zchenhn at gmail.com> wrote: > >> Hello, >> >> I want to disable LLVM to use any SIMD registers like sse and avx. I >> tried -mno-sse and -mno-avx on my Core i7 machine. It seems that the >> generated assembly still uses xmm registers. Is there any way for LLVM to >&g...

Yes. That's what I was the solution in my mind. But I just wanted to know if there was a generic way to save some code... On Thu, Apr 16, 2015 at 8:32 PM, Tim Northover <t.p.northover at gmail.com> wrote: > > I understand that I can detect the operation first, and use "create" to > > create for each of them. But I don't if there is a generic way to do this

...ews.llvm.org/D16528 / http://reviews.llvm.org/rL258675 On Wed, Feb 24, 2016 at 11:39 PM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > Yes, masked load/store/gather/scatter are completed. > > > > - * Elena* > > > > *From:* zhi chen [mailto:zchenhn at gmail.com] > *Sent:* Thursday, February 25, 2016 01:20 > *To:* Demikhovsky, Elena <elena.demikhovsky at intel.com> > *Cc:* Sanjay Patel <spatel at rotateright.com>; Nema, Ashutosh < > Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> > > *...