search for: zbc

From: Thierry Reding <treding at nvidia.com> gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c | 2 +- drivers...

Due to the lack of implicit synchronization between CPU and GPU on Tegra systems (like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B relied on the slow, legacy PRAMIN so that CPU accesses used the same path as GPU, making sure we see the same data on both ends. The recent Nouveau refactoring introduced acquire/release functions on instmem that help us understand the

...) } W <- function(G){ G11 <- G[1:n, 1:4] G12 <- G[1:4, 5:6] G22 <- G[5:6, 5:6] } W <- function(G,n,k){ G11 <- G[1:n, 1:n] G12 <- G[1:n, (n+1):(n+k)] G22 <- G[(n+1):(n+k), (n+1):(n+k)] G11 - G12 %*% solve(G22) %*% t(G12) } zbc <- function(y,lambda, mu, sigma) { ((y/mu)^lambda - 1) / (lambda * sigma) } L1 <- function(y,lambda, mu, sigma) { z <- zbc(y,lambda, mu, sigma) return(z/(mu * sigma) + lambda * (z^2 - 1) / mu) } L2 <- function(y,lambda,mu,sigma){ z <- zbc(y,lambda, mu, s...

...t; + if (taken > 0) > + nvkm_debug(&ltc->subdev, "LTC flush took %lld ns\n", taken); > +} > + > /* TODO: Figure out tag memory details and drop the over-cautious allocation. > */ > int > @@ -215,6 +249,8 @@ gf100_ltc = { > .zbc = 16, > .zbc_clear_color = gf100_ltc_zbc_clear_color, > .zbc_clear_depth = gf100_ltc_zbc_clear_depth, > + .invalidate = gf100_ltc_invalidate, > + .flush = gf100_ltc_flush, > }; > > int > diff --git a/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drm/nou...

...ect good 0a5b97304b9e2cd07c78a399c5395d5fb0118341 # good: [18d17221dd58741a8590ba0a40a9ded82aa5d619] drm/nouveau/gr/gf100-: virtualise r419e00 git bisect good 18d17221dd58741a8590ba0a40a9ded82aa5d619 # good: [e9d03335f604a1123b8de3103ce8e06db4ad777a] drm/nouveau/gr/gp100-: use correct registers for zbc colour/depth setup git bisect good e9d03335f604a1123b8de3103ce8e06db4ad777a # good: [512fa0b8a398539c3c2db251f6c40da4ef065d09] drm/nouveau/drm/nv50-: remove allocation of sw class git bisect good 512fa0b8a398539c3c2db251f6c40da4ef065d09 # good: [62b290fc7b36e8fec2a370b946d7117c1899b6c1] drm/nouveau...

.../nouveau_drm.h +++ b/drivers/gpu/drm/nouveau/nouveau_drm.h @@ -10,7 +10,7 @@ #define DRIVER_MAJOR 1 #define DRIVER_MINOR 2 -#define DRIVER_PATCHLEVEL 0 +#define DRIVER_PATCHLEVEL 1 /* * 1.1.1: @@ -26,6 +26,8 @@ * 1.2.0: * - object api exposed to userspace * - fermi,kepler,maxwell zbc + * 1.2.1: + * - allow concurrent access to bo's mapped read/write. */ #include <nvif/client.h> -- 2.0.4

...304b9e2cd07c78a399c5395d5fb0118341 > # good: [18d17221dd58741a8590ba0a40a9ded82aa5d619] drm/nouveau/gr/gf100-: virtualise r419e00 > git bisect good 18d17221dd58741a8590ba0a40a9ded82aa5d619 > # good: [e9d03335f604a1123b8de3103ce8e06db4ad777a] drm/nouveau/gr/gp100-: use correct registers for zbc colour/depth setup > git bisect good e9d03335f604a1123b8de3103ce8e06db4ad777a > # good: [512fa0b8a398539c3c2db251f6c40da4ef065d09] drm/nouveau/drm/nv50-: remove allocation of sw class > git bisect good 512fa0b8a398539c3c2db251f6c40da4ef065d09 > # good: [62b290fc7b36e8fec2a370b946d7117c1...

...*/ + cancel_work_sync(&pmu->isr_workq); + pmu->initialized = false; + + mutex_lock(&pmu->isr_mutex); + pmu_enable(ppmu, pmc, false); + pmu->isr_enabled = false; + mutex_unlock(&pmu->isr_mutex); + + pmu->pmu_state = PMU_STATE_OFF; + pmu->pmu_ready = false; + pmu->zbc_ready = false; + + return 0; +} + +int gk20a_pmu_load_norm(struct nvkm_pmu *ppmu, u32 *load) +{ + struct nvkm_pmu_impl *impl = (void *)nv_oclass(ppmu); + struct pmu_desc *pmu = &impl->pmudata; + *load = pmu->load_shadow; + return 0; +} + +int gk20a_pmu_load_update(struct nvkm_pmu *ppmu) +...

...gt; + mutex_lock(&pmu->isr_mutex); > + pmu_enable(ppmu, pmc, false); > + pmu->isr_enabled = false; > + mutex_unlock(&pmu->isr_mutex); > + > + pmu->pmu_state = PMU_STATE_OFF; > + pmu->pmu_ready = false; > + pmu->zbc_ready = false; > + > + return 0; > +} > + > +int gk20a_pmu_load_norm(struct nvkm_pmu *ppmu, u32 *load) > +{ > + struct nvkm_pmu_impl *impl = (void *)nv_oclass(ppmu); > + struct pmu_desc *pmu = &impl->pmudata; > + *load = pmu->load_shadow;...

...gt; + mutex_lock(&pmu->isr_mutex); > + pmu_enable(ppmu, pmc, false); > + pmu->isr_enabled = false; > + mutex_unlock(&pmu->isr_mutex); > + > + pmu->pmu_state = PMU_STATE_OFF; > + pmu->pmu_ready = false; > + pmu->zbc_ready = false; > + > + return 0; > +} > + > +int gk20a_pmu_load_norm(struct nvkm_pmu *ppmu, u32 *load) > +{ > + struct nvkm_pmu_impl *impl = (void *)nv_oclass(ppmu); > + struct pmu_desc *pmu = &impl->pmudata; > + *load = pmu->load_shadow;...

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

...0 { + __u8 version; + __u8 pad01[7]; + __u64 time; +}; +#endif diff --git a/nouveau/nvif/cl9097.h b/nouveau/nvif/cl9097.h new file mode 100644 index 0000000..4057676 --- /dev/null +++ b/nouveau/nvif/cl9097.h @@ -0,0 +1,44 @@ +#ifndef __NVIF_CL9097_H__ +#define __NVIF_CL9097_H__ + +#define FERMI_A_ZBC_COLOR 0x00 +#define FERMI_A_ZBC_DEPTH 0x01 + +struct fermi_a_zbc_color_v0 { + __u8 version; +#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 +#define FERMI_A_ZBC_COLOR_...

From: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> --- nouveau/abi16.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++----- nouveau/nouveau.c | 56 +++++++------------------------------------------ nouveau/private.h | 7 ++----- 3 files changed, 67 insertions(+), 58 deletions(-) diff --git a/nouveau/abi16.c b/nouveau/abi16.c index

...0 { + __u8 version; + __u8 pad01[7]; + __u64 time; +}; +#endif diff --git a/nouveau/nvif/cl9097.h b/nouveau/nvif/cl9097.h new file mode 100644 index 0000000..4057676 --- /dev/null +++ b/nouveau/nvif/cl9097.h @@ -0,0 +1,44 @@ +#ifndef __NVIF_CL9097_H__ +#define __NVIF_CL9097_H__ + +#define FERMI_A_ZBC_COLOR 0x00 +#define FERMI_A_ZBC_DEPTH 0x01 + +struct fermi_a_zbc_color_v0 { + __u8 version; +#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 +#define FERMI_A_ZBC_COLOR_...

...gY6qDdZk8s2ZbG0uYZ11wdUkouVhmSPACMRH3u17rLkhSF4kTx OdTfLZ9uSjl7r0C76lxR1470brvMEGjH3gTZ6+nlw4nkh4P1IVGLrDqSlBX7dMsc8nVWyHXm XZjnGlhdRxFoB1e8QgfQDtXI3TGR3ikldhmrPa0Wo7pGW/cMkdG6ZlPJ7vpk13uPGtgW2nS/ NOtjR3G202ZPPG1Tg/YbgPYbTNSvHh6DiWj5ci8owr1RShs97qaUo4+a2VC7Mt3scPv5TOkk aFd8cnCCXAwlf4XBAo5lBmhX/laaipzBcGufBO0sB5fPRJuUErurWAiWT6zqKtuGM8f8D2WX 68iVlc2oTNcY6qDdZk/a7uqCj6pA9kgdVkoSq/DzkOSxx03umnSdicsSvqE4QYQHZvR3xaeb EvOHyhQPwRYS27UjvUddxvZ0a3VSWVJi1jO7PiRqkauOKGXFPhOcVvR1rgcrMu/CPNfA6jpy OwIcEXV5xvBJeIyr9yim3YJ2a7RDniEyWnfcrGSPfLL13qMGtro2rdEOebAh5KOyJwNfU4P2 IdC+2+3p33LEngexRxtRbwnaeTZDrVUdrm9GtrjXT...

...7G;$iQ|9ttLC+6L1BGDrqUhbQ> zbIxCOziYJKOO-P2UhAQuT~H?&a&>iAUo9q|HTTa9&koP1oK=xklKn8)qqP4hL<K}g zZbGAPqN;1uNqS&R^uQYr+}mo+9{<31UVr$iYe|%YOq3Po?YZ}k-2>V-Itw9kwcUao z?PT}Dy8JQYB-RRTmi_D>BTv5&e({fgex41Ne+R8I1SkVc0$iQV*k5uOD~5f!wFzTK z0HsiqcL56X7<&-#Pry*XXuv$cuzbcA0R}Z?Y+3<hjbJ$+0yJsC*b{(nuVAcoOUCX8 z3<OLDYzCYFth|ab^%`gpfL~n8*tLbwZU7$xz5;B&jxqUq2s*$^fC+%5fd6XE*hhf( ziWqC$hOxVf8QTOXXvf%1fSG{PfCcT551?5G-~hS<o&yX7Oad$dR0DJq_<)ri8Jl|} zV=s1MY&YOXH!-#m at HybIn_(#e-T;jH5o29%VT|93vfaj5o7)+i4p?>vV@>a5Yzd$d ztp6#1J%H!$V(fLmukS`#0quXn*kZ...