search for: yulin

...ould be better to have a more generic scheme in LLVM. From: Chris Lattner [mailto:clattner at apple.com] Sent: Monday, December 17, 2012 12:48 PM To: Yuan Lin Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] target specific ways to extend ConstantExpr On Dec 17, 2012, at 11:26 AM, Yuan Lin <yulin at nvidia.com<mailto:yulin at nvidia.com>> wrote: I am looking for a way to allow ConstantExpr to express target specific operations, which will be used in global initializers. The recommended way to extend LLVM IR is using intrinsic functions. But this does not work for ConstantExpr, w...

...) and a list of operands? The first operand is a string. From: Chris Lattner [mailto:clattner at apple.com] Sent: Monday, December 17, 2012 4:39 PM To: Yuan Lin Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] target specific ways to extend ConstantExpr On Dec 17, 2012, at 4:23 PM, Yuan Lin <yulin at nvidia.com<mailto:yulin at nvidia.com>> wrote: The particular case we are looking at is converting a pointer from one address space to another address space. There is one operand and one output, both are the same pointer type, except for their address space. The pointers are of the sa...

On Dec 17, 2012, at 4:23 PM, Yuan Lin <yulin at nvidia.com> wrote: > The particular case we are looking at is converting a pointer from one address space to another address space. There is one operand and one output, both are the same pointer type, except for their address space. The pointers are of the same size. The operation is a bi...

On Dec 17, 2012, at 11:26 AM, Yuan Lin <yulin at nvidia.com> wrote: > I am looking for a way to allow ConstantExpr to express target specific operations, which will be used in global initializers. > > The recommended way to extend LLVM IR is using intrinsic functions. But this does not work for ConstantExpr, which the global ini...

I am looking for a way to allow ConstantExpr to express target specific operations, which will be used in global initializers. The recommended way to extend LLVM IR is using intrinsic functions. But this does not work for ConstantExpr, which the global initializer uses. Should we make ConstantExpr to support some kind of side-effect free intrinsic function calls? If we want to work on such a

On Mon, Dec 17, 2012 at 5:10 PM, Yuan Lin <yulin at nvidia.com> wrote: > We cannot use bitcast because bitcast is a value preserving operation, but > the address space conversion operation we have is a bit-changing operation. > > > > Where will the bulk of work be? Can we make a ConstantExpr which has a new > Opcode (or re...

...Yuan -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Monday, December 17, 2012 5:40 PM To: Yuan Lin Cc: Chris Lattner; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] target specific ways to extend ConstantExpr On Mon, Dec 17, 2012 at 5:10 PM, Yuan Lin <yulin at nvidia.com> wrote: > We cannot use bitcast because bitcast is a value preserving operation, > but the address space conversion operation we have is a bit-changing operation. > > > > Where will the bulk of work be? Can we make a ConstantExpr which has a > new Opcode (or...

Fix the return value of blkdev_name_to_number(). - Function blkdev_name_to_number() should return both devname and devnum, otherwise it may cause "unpack non-sequence" error. Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com> Best Regards, -- Dongxiao _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

...able priority to fix it (or at least put an NYI assertion!). It seems to be quite more complex, than implementing custom lowering handler, that's why I'm not trying myself. So for now I filled a bug, just for record: http://llvm.org/bugs/show_bug.cgi?id=13291 - Dima. 2012/7/3 Yuan Lin <yulin at nvidia.com>: > In our (NVIDIA’s) NVVM IR spec, we define i1 having a memory size of 8 bit. > > > > setOperationAction(ISD::LOAD, MVT::i1, Custom); > > setOperationAction(ISD::STORE, MVT::i1, Custom); > > > > is the right way to go. > > > > Yuan...

Yes, it helps a lot and we are working on it. A few questions, 1) What will be your use model of this library? Will you run optimization phases after linking with the library? If so, what are they? 2) Do you care if the names of functions differ from those in libm? For example, it would be gpusin() instead of sin(). 3) Do you need a different library for different host

...epth. Moving this part only on our own would slow down the progess with main targets too much, that's why I'm asking for your help and cooperation. Best regards, - Dima. [1] https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen 2013/2/8 Yuan Lin <yulin at nvidia.com> > Yes, it helps a lot and we are working on it.**** > > ** ** > > A few questions,**** > > **1) **What will be your use model of this library? Will you run > optimization phases after linking with the library? If so, what are they?* > *** > >...

...ld slow down the progess with > main targets too much, that's why I'm asking for your help and cooperation. > > Best regards, > - Dima. > > [1] > https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen > > 2013/2/8 Yuan Lin <yulin at nvidia.com> > >> Yes, it helps a lot and we are working on it.**** >> >> ** ** >> >> A few questions,**** >> >> **1) **What will be your use model of this library? Will you run >> optimization phases after linking with the library? If so...

...t; main targets too much, that's why I'm asking for your help and cooperation. >> >> Best regards, >> - Dima. >> >> [1] >> https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen >> >> 2013/2/8 Yuan Lin <yulin at nvidia.com> >> >>> Yes, it helps a lot and we are working on it.**** >>> >>> ** ** >>> >>> A few questions,**** >>> >>> **1) **What will be your use model of this library? Will you run >>> optimization phases a...

...39;s why I'm asking for your help and cooperation. >>> >>> Best regards, >>> - Dima. >>> >>> [1] >>> https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen >>> >>> 2013/2/8 Yuan Lin <yulin at nvidia.com> >>> >>>> Yes, it helps a lot and we are working on it.**** >>>> >>>> ** ** >>>> >>>> A few questions,**** >>>> >>>> **1) **What will be your use model of this library? Will you run &g...

...help and cooperation. >>>> >>>> Best regards, >>>> - Dima. >>>> >>>> [1] >>>> https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen >>>> >>>> 2013/2/8 Yuan Lin <yulin at nvidia.com> >>>> >>>>> Yes, it helps a lot and we are working on it.**** >>>>> >>>>> ** ** >>>>> >>>>> A few questions,**** >>>>> >>>>> **1) **What will be your use model...

In ptx, variables need to be defined before referenced. NVPTX emits the global variables in the order as in the LLVM IR and does not sort them. It is a bug in the NVPTX backend. Thanks. Yuan From: Dmitry N. Mikushin [mailto:maemarcus at gmail.com] Sent: Wednesday, July 18, 2012 7:44 AM To: LLVM-Dev Cc: Justin Holewinski; Yuan Lin Subject: [NVPTX] PTXAS - Unimplemented feature: labels as

...gt;>> >>>>> Best regards, >>>>> - Dima. >>>>> >>>>> [1] >>>>> https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen >>>>> >>>>> 2013/2/8 Yuan Lin <yulin at nvidia.com> >>>>> >>>>>> Yes, it helps a lot and we are working on it.**** >>>>>> >>>>>> ** ** >>>>>> >>>>>> A few questions,**** >>>>>> >>>>>> **1)...

...>> Best regards, >>>>>> - Dima. >>>>>> >>>>>> [1] >>>>>> https://hpcforge.org/scm/viewvc.php/*checkout*/trunk/src/cuda/include/math.bc?root=kernelgen >>>>>> >>>>>> 2013/2/8 Yuan Lin <yulin at nvidia.com> >>>>>> >>>>>>> Yes, it helps a lot and we are working on it.**** >>>>>>> >>>>>>> ** ** >>>>>>> >>>>>>> A few questions,**** >>>>>>> >&...

Dear NVPTX community, PTXAS fails to compile the ptx code generated by NVPTX. Is it an issue of backend or an issue of PTXAS or a known reasonable restriction? Thanks, - Dima. > cat test.ll ; ModuleID = '__kernelgen_main_module' target datalayout = "e-p:64:64-i64:64:64-f64:64:64-n1:8:16:32:64" target triple = "ptx64-unknown-unknown" %struct.__st_parameter_dt.0.4

In our (NVIDIA's) NVVM IR spec, we define i1 having a memory size of 8 bit. setOperationAction(ISD::LOAD, MVT::i1, Custom); setOperationAction(ISD::STORE, MVT::i1, Custom); is the right way to go. Yuan From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Justin Holewinski Sent: Monday, July 02, 2012 9:55 AM To: Dmitry N. Mikushin Cc: llvmdev at