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...ng the same tile. Hal, for your suggestion would which physical registers are in which register class be defined dynamically before register allocation? From: Hal Finkel <hfinkel at anl.gov> Sent: Wednesday, August 19, 2020 12:52 PM To: Kaylor, Andrew <andrew.kaylor at intel.com>; Luo, Yuanke <yuanke.luo at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion....

...e used to create the actual tile configuration. The instructions that need to know the shape take these runtime values as operands. There may be some artifacts coming from the front end that conservatively assume a 16x16 tile, but I think those generally go away in SROA or later specialized passes. Yuanke can confirm or correct my understanding of this. From: Hal Finkel <hfinkel at anl.gov> Sent: Wednesday, August 19, 2020 5:14 AM To: Luo, Yuanke <yuanke.luo at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at...

From: Hal Finkel <hfinkel at anl.gov> Sent: Friday, August 14, 2020 11:27 PM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion....

...d64 and deduce the shape of %0 is %row x %col. %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %col, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32) From: Hal Finkel <hfinkel at anl.gov> Sent: Wednesday, August 19, 2020 4:58 PM To: Luo, Yuanke <yuanke.luo at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [...

...ng, a little example would be helpful. Thanks again, Hal > ~Craig > > *From:* Hal Finkel <hfinkel at anl.gov> > *Sent:* Thursday, August 20, 2020 12:35 PM > *To:* Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew > <andrew.kaylor at intel.com>; Luo, Yuanke <yuanke.luo at intel.com>; Philip > Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; > florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> > *Subject:* Re: [llvm-dev] Intel AMX programming model discussion. > > On 8/19/20 3:09 PM, T...

...tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 $tmm0 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg $tmm1 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg $tmm2 = TILELOADDV %17:gr64, 1, %18:gr64_nosp, 0, $noreg $tmm2 = TDPBSSDV $tmm2(tied-def 0), $tmm0, $tmm1 Thanks Yuanke From: Hal Finkel <hfinkel at anl.gov> Sent: Friday, August 21, 2020 3:35 AM To: Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Luo, Yuanke <yuanke.luo at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at li...

...tion for the patch, I'd like to land it. [1] http://lists.llvm.org/pipermail/llvm-dev/2020-August/143972.html [2] http://lists.llvm.org/pipermail/llvm-dev/2020-August/144302.html [3] http://lists.llvm.org/pipermail/llvm-dev/2020-September/145200.html [4] https://reviews.llvm.org/D87981 Thanks Yuanke -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20201119/912b84fb/attachment.html>

...3. The tile configure is to configure physical tile register, so we need to allocate register and then we know the shape of each physical tile register and configure the tile register. I think your suggestion is helpful to reduce the complexity if we only support fixed (constant) tile shape. -Yuanke From: Hal Finkel <hfinkel at anl.gov> Sent: Wednesday, August 19, 2020 8:20 AM To: Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Toppe...

Fix typo From: Luo, Yuanke Sent: Friday, September 4, 2020 9:47 PM To: 'Hal Finkel' <hfinkel at anl.gov>; Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com...

Hi Philip, Your idea make sense to me in my first thought. Thank you for the idea. I will take more time to think it over to see it can help to reduce the complexity of tile register allocation. Yuanke From: Philip Reames <listmail at philipreames.com> Sent: Saturday, August 15, 2020 11:29 AM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com&g...

On 9/4/20 3:37 AM, Luo, Yuanke wrote: > > Hi Hal, > > Thank you for the ideas that help us to improve the design, and sorry > for replying late. There is something I am not able to figure out and > there some special trait for tile RA. > You're quite welcome. > 1.X86RegisterInfo::getRegAllocatio...

...we don't need to do anything especially clever. We can just do something straightforward that is correct and let the user know that they aren't going to be happy with the results. -Andy From: Philip Reames <listmail at philipreames.com> Sent: Friday, August 14, 2020 8:29 PM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion....

[Yuanke] AMX register is special. It needs to be configured before use and the config instruction is expensive. To avoid unnecessary tile configure, we collect the tile shape information as much as possible and combine them into one ldtilecfg instruction. The ldtilecfg instruction should dominate any AMX...

Hi, Yuanke, Thanks for writing this up. Let me back up a bit because the scheme I proposed last week doesn't work without further modification: within a particular "configuration region" (i.e., the code in between the LDTILECFG and the TILERELEASE (or next LDTILECFG)), each tile register c...

...ognize. But forcing users to rewrite “rep;stosb”->“rep stosb” doesn’t seem productive. -Eli From: Philip Reames <listmail at philipreames.com> Sent: Wednesday, March 25, 2020 1:34 PM To: Eric Christopher <echristo at gmail.com>; Eli Friedman <efriedma at quicinc.com> Cc: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev <llvm-dev at lists.llvm.org>; Zhang, Annita <annita.zhang at intel.com>; Craig Topper <craig.topper at intel.com> Subject: [EXT] Re: [llvm-dev] Status of Intel JCC Mitigations and Next Steps The slightly unexpected bit for me in these r...

Hi Yuanke, As I said on the review, I think at least Craig should have a look and approve before landing, as this is a major change in the x86 back-end. cheers, --renato On Thu, 19 Nov 2020 at 02:29, Luo, Yuanke via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > > > Several...

...> the rules are documented. > > > > -Eli > > > > *From:* llvm-dev <llvm-dev-bounces at lists.llvm.org> *On Behalf Of *Philip > Reames via llvm-dev > *Sent:* Tuesday, March 24, 2020 3:55 PM > *To:* llvm-dev <llvm-dev at lists.llvm.org> > *Cc:* Luo, Yuanke <yuanke.luo at intel.com>; Zhang, Annita < > annita.zhang at intel.com>; Craig Topper <craig.topper at intel.com> > *Subject:* [EXT] [llvm-dev] Status of Intel JCC Mitigations and Next Steps > > > > TLDR - We have a choice to make about assembler support, and a...

...Use recommendation Due to the shape configure issue, we recommend user to define the tile shape at the entry of the function entry and inline function as much as possible. The AMX instructions focus on computation instead of storage, so global variable for tile data is not recommended. Thanks Yuanke -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200814/a6104f3b/attachment.html>

Hi Xiang, On Wed, Nov 11, 2020 at 1:59 AM Zhang, Xiang1 <xiang1.zhang at intel.com> wrote: > Jeremy wrote: > > ... The value %0 is live up to and including the ADD64ri but not past it, meaning LLVM today will drop the DBG_VALUE ... > > Just a little puzzle about the " drop the DBG_VALUE ", maybe I didn't get your key point, >

TLDR - We have a choice to make about assembler support, and a disagreement about how to move forward.  Community input needed. Background Intel has a hardware bug in Skylake and later whose mitigation requires padding of branches to avoid performance degradation. Background here: