search for: yourtargetregisterinfo

Displaying 9 results from an estimated 9 matches for "yourtargetregisterinfo".

2014 Jun 20
3
[LLVMdev] Passing specific register for an Instruction in target description files.
Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name
2014 Jul 02
2
[LLVMdev] Passing specific register for an Instruction in target description files.
...gt; > May be someone could help with an example? > > If I understood correctly, you want your instruction to define a specific register. > If yes, you can achieve this by creating a specialized singleton register class with the register you want and use it in the td file. > E.g., in yourTargetRegisterInfo.td: > def MyReg : RegisterClass<“MyTarget”, [Related Types], MySize, (add MyReg)>; > > in yourTargetInstrInfo.td: > def MyInstr […] (outs MyReg:$Rd) […] > > The ARM target does something similar for SP. Look for GPRsp. > If you use this approach, you may run into issu...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...p.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the SimpleValueType to define the register class instead of the actual register class defined in the td? What am I missing here? Right now, the types are bound to register classes. See YourTargetRegisterInfo.td for the description of that mapping. I believe that we first create a VReg using that RC then constraint it with the RC in the td. Two things: 1. You can point me where you saw that and I can give you the exact meaning of the snippet. 2. You can change the mapping of your type in your RegisterIn...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...is it using the SimpleValueType to define the >>>> register class instead of the actual register class defined in the td? What >>>> am I missing here? >>>> >>>> >>>> Right now, the types are bound to register classes. See >>>> YourTargetRegisterInfo.td for the description of that mapping. I believe >>>> that we first create a VReg using that RC then constraint it with the RC in >>>> the td. >>>> Two things: >>>> 1. You can point me where you saw that and I can give you the exact >>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...alueType to define the >>>>> register class instead of the actual register class defined in the td? What >>>>> am I missing here? >>>>> >>>>> >>>>> Right now, the types are bound to register classes. See >>>>> YourTargetRegisterInfo.td for the description of that mapping. I believe >>>>> that we first create a VReg using that RC then constraint it with the RC in >>>>> the td. >>>>> Two things: >>>>> 1. You can point me where you saw that and I can give you the exact &...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...gt;>>>>> register class instead of the actual register class defined in the td? What >>>>>> am I missing here? >>>>>> >>>>>> >>>>>> Right now, the types are bound to register classes. See >>>>>> YourTargetRegisterInfo.td for the description of that mapping. I believe >>>>>> that we first create a VReg using that RC then constraint it with the RC in >>>>>> the td. >>>>>> Two things: >>>>>> 1. You can point me where you saw that and I can give...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...gt; register class instead of the actual register class defined in the td? What >>>>>>> am I missing here? >>>>>>> >>>>>>> >>>>>>> Right now, the types are bound to register classes. See >>>>>>> YourTargetRegisterInfo.td for the description of that mapping. I believe >>>>>>> that we first create a VReg using that RC then constraint it with the RC in >>>>>>> the td. >>>>>>> Two things: >>>>>>> 1. You can point me where you saw tha...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...nstead of the actual register class defined in the td? What >>>>>>>> am I missing here? >>>>>>>> >>>>>>>> >>>>>>>> Right now, the types are bound to register classes. See >>>>>>>> YourTargetRegisterInfo.td for the description of that mapping. I believe >>>>>>>> that we first create a VReg using that RC then constraint it with the RC in >>>>>>>> the td. >>>>>>>> Two things: >>>>>>>> 1. You can point me w...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Quentin, This is the issue. Somewhere prior to the constrainRegClass, it's assigning the GPRBase sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in favor of it's sub class GPR. Thanks. On Mon, Aug 24, 2015 at 8:34 PM, Ryan Taylor